FUNCTION OF COMBINATIONAL LOGIC CIRCUIT CHAPTER 4 FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

Subtopics 4.1 Half-Adder and Full-Adder Circuit 4.2 4-bit Parallel Binary Ripple Carry Adder Circuit 4.3 4-bit Parallel Binary Look Ahead Carry Adder Circuit 4.4 BCD Adder Circuit 4.5 Decoder & Encoder 4.6 Multiplexer & Demultiplexer 4.7 Comparator 4.8 Code Converters 4.9 Parity Generator and Checker Circuit

Learning Outcome At the end of this topic, you should be able to: Explain the function of the special combinational logic circuits, i.e. HA, FA, decoder, encoder, etc. (see subtopic) Analyse the circuit using these special combinational logic circuits. Design a circuit using these special combinational logic circuits.

4.1 Half-adder (HA) and Full-adder (FA) Circuits Let us revise on the basic binary operations… An adder circuit will add up two 1-bit binary numbers that produces the sum and carry. Difference between HA and FA: FA has a carry in input Addition 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 Addition Carry Sum 0 + 0 0 + 1 1 1 + 0 1 + 1

Half-adder (HA) A half-adder accepts 2 binary digits on its inputs (e.g. A and B) and produces two binary digits on its outputs (i.e. 1-bit SUM and 1-bit CARRY) Its logic symbol is given by

Therefore, logic circuit of HA is Its truth table is Therefore, logic circuit of HA is Input Output A B Cout  1  = A  B = AB’ +A’B Cout = A  B

Full-adder (FA) A full-adder accepts two input bits (A & B) and an input carry (Cin) and generates a sum output and an output carry.

The truth table of FA is: Input Output A B Cin  Cout 1  = A  B  Cin Cout = AB + (A  B) Cin

 = A’B’Cin + AB’Cin’ + A’BCin’ + ABCin = B’(A’Cin+ACin’) + B(A’Cin’+ACin) = B’(A  Cin) + B(A  Cin)’ = B  (A  Cin) = A  B  Cin Cout = A’BCin + AB’Cin + ABCin’ +ABCin = Cin (A’B + AB’) + AB(Cin’ + Cin) = Cin (A  B) + AB

From this, we could draw the combinational logic circuit to represent this adder. A  B  = A  B  Cin Cout = AB + (A  B) Cin

Rearrange it, actually it comprises of 2 HAs & 1 OR gate.

4.2 4-bit Parallel Binary Ripple Carry Adder What is 4-bit Parallel Binary Ripple Carry Adder? A circuit that does the addition of 4-bit binary number (A4,A3,A2,A1) with another 4-bit binary number (B4,B3,B2,B1) & produces the outputs of 4-bit SUM (4,3,2,1) and 1-bit Carry Out (C4) The block diagram

FA can be connected together to perform addition in parallel of two multibit binary numbers. Therefore, to form a 4-bit parallel binary ripple carry adder, the 4 full adders are cascaded. The carry-in C0 must be connected to GND (i.e. 0) Notice that the carry out in stage 0  carry in for stage 1 and so forth, (behaving in similar way as ripple  the term ripple is used here)

Operation of a 4-bit parallel binary ripple carry adder Example: If register A = 0111 and register B = 1101 are applied to a 4-bit parallel ripple carry adder, what are the resulting outputs of SUM and C4? 1 1 1 1 1 Sum = 0100 & C4 = 1

How to implement a SUBTRACTOR using an ADDER? REVISION: Subtraction of signed numbers could be emulated as the addition the number with that of 2’s complement of the subtrahend. To change binary number into 2’s complement: step 1: invert all the bits use NOT gate step 2: add 1 how?!! => there is a better way to implement this!! minuend  subtrahend difference minuend + subtrahend (2’s complement) result Negative number

Implementing A Subtractor from An Adder Use XOR gate: Control bit B Cout 1 ADDER/SUBTRACTOR This is a control signal. For this device to operate as a subtractor, set this control signal to 1. If it is set to 0, the device will perform an addition instead.

4 bit binary number, B and control signal  form the 2’s complement representation of __ number B.

EXAMPLE What are the resulting output of SUM and C4 if [A]=0101 is subtracted with [B]=0001? 1 1 1 1 1 1 1 SUM = 0100 & Co = 1

Commercial IC for 4-bit parallel adder is… 74LS283

4.3 4-bit Parallel Binary Look Ahead Carry Adder The look-ahead carry adder is used to eliminate the relatively slow rippling effect of the carry bits of the carry adder. Look Ahead Carry anticipates the output carry of each stage and based on the inputs, produces the output carry by either carry generation or carry propagation.

Carry generation occurs when an output carry is produced internally by the FA. Cg = AB Carry propagation occurs when the input carry is rippled to become output carry. Cp = A + B Therefore, the output carry of a full adder can be expressed as Cout = Cg + CpCin

Apply these equations to a ripple adder Cout3 = Cin3.Cp3 +Cg3 Cout1 = Cin1.Cp1 +Cg1 Cout4 = Cin4.Cp4 +Cg4 Cout2 = Cin2.Cp2 +Cg2

Full-adder 1: Cout1 = Cg1 + Cp1Cin1 Full-adder 2: Cin2 = Cout1 Cout2 = Cg2 + Cp2Cin2 = Cg2 + Cp2Cout1 = Cg2 + Cp2Cg1+ Cp2Cp1Cin1 Full-adder 3: Cin3 = Cout2 Cout3 = Cg3 + Cp3Cin3 = Cg3 + Cp3Cout2 = Cg3 + Cp3Cg2+ Cp3Cp2Cg1+ Cp3Cp2Cp1Cin1 Full-adder 4: Cin4 = Cout3 Cout4 = Cg4 + Cp4Cin4 = Cg4 + Cp4Cout3 = Cg4 + Cp4Cg3 + Cp4Cp3Cg2 + Cp4Cp3Cp2Cp1Cg1 + Cp4Cp3Cp2Cp1Cin1

Therefore, the look-ahead adder is Cin2 = Cout1 Therefore, the look-ahead adder is Cg1 Cp1

Example If register A = 0111 and register B = 1101 are applied to a 4-bit parallel look ahead carry adder, what are the resulting outputs of SUM and C4? 1 Cout4=1 1 1  i.e. SUM = 0100

4.4 BCD Adder BCD ADDER is an adder that performs an addition of two BCD numbers. The resultant is shown also in BCD format. To represent 1 digit BCD adder, a 4-bit parallel adder is used. (A4A3A2A1) represent 1 digit BCD  input (B4B3B2B1) represent another 1 digit BCD  input 4 bit sum to represent the result  output 1 bit ‘carry’ if sum is more than 9  output

i) illegal codes in BCD (i.e. 1010, 1011, 1100, 1101, 1110 & 1111) However, the resultant of these two BCD numbers may not be in the right form under these two conditions (in which the outcome exceeds value of 9 in decimal) : i) illegal codes in BCD (i.e. 1010, 1011, 1100, 1101, 1110 & 1111) ii) value exceeds 4 bits (when the resultant sum contains a __ carry, C4 = 1) We need a correction circuit to overcome this situation. It requires 2 units of 74LS283 (4-bit parallel adder) & a checker 1 unit adder to perform the addition A checker whether the resultant is > 9 (see above). X = C4 + S4 S3 + S4 S3’ S2 = C4 + S4 (S3 + S3’S2) = C4 + S4 (S3 + S2) Another 1 unit adder for correction purpose. If X is true, addition of 6 (i.e. 01102) is added to the sum of BCD adder. If X is false, no addition will be performed (i.e. 00002 is added)

Checker: if x is true, then addition of 6 will be performed.

Example 1001 (BCD) is added to 1001 (BCD) using a BCD adder. What are the outcomes at the SUM and C4? 1 0 0 1 0 0 1 0 1 0 0 0 NOTE: In decimal, 9+9 = 18. Therefore, the least significant digit is 8 = 1000 (BCD) 1 0 0 1 0 1 1 0 1 1 0110 is added as the voltage level of this line becomes high (true)

Active-high and active-low concepts Concept of active logic levels : Active-HIGH when an input or output line has no bubble on it. Active-LOW when an input or output line has a bubble on it Thus, the presence of the bubble will determine its active status Example: A decoder with ACTIVE LOW outputs

4.5(a) Decoder (BM: Penyahkod) A decoder is a circuit that detects the presence of a specified combination of bits (code) on its inputs and indicates the presence of that code by a specified output level. If a decoder has n input lines, the number of output lines are 2n. Block diagram of a decoder

Basic Binary Decoder For a 2-to-4 decoder, the truth table is: From this truth table, the CL is A1 A0 O0 O1 O2 O3 1

For a 3-to-8 decoder, the truth table is: 1 This is an ACTIVE HIGH output. If the output is ACTIVE LOW, just INVERT the output bits.

Thus, the CL for 3-to-8 decoder (ACTIVE HIGH) is If decoder is an ACTIVE LOW type, replace AND gates with NAND gates (as shown in the module).

Commercial ICs for decoders 3-to-8 decoder  74LS138 (this is an ACTIVE LOW output)

Internal circuitry of a 3-to-8 decoder  74LS138

Commercial ICs for decoders 4-to-16 decoder  74HC154 (this is an ACTIVE LOW output)

Commercial ICs for decoders BCD-to-Decimal Decoder a.k.a 4-to-10 decoder  74HC42 (this is also an ACTIVE LOW output)

Commercial ICs for decoders BCD-to-7-segment Decoder  74HC47 (also active LOW outputs) LT is used for lamp test (when BI/RBO is high). RBI (Ripple Blanking Input) and BI/RBO (Blanking Input/Ripple Blanking Output) are used for zero suppression.

4.5(b) Encoder (BM: Pengekod) An encoder is a CL that generates an M-bit binary code that uniquely identifies the activated input i.e. inverse function of decoder Only 1 input can be activated at 1 time. If not, the circuit has no meaning.

Decimal-to-BCD Encoder BCD are binary codes that represent digit 0 to 9. Decimal Input BCD code A3 A2 A1 A0 1 2 3 4 5 6 7 8 9

Decimal-to-BCD Priority Encoder Priority encoder allows the activation of several inputs simultaneously, but only the highest input number is encoded. Commercial IC available  74HC147 ACTIVE-LOW for both inputs & outputs

8-to-3 Priority Encoder Could be used as a conversion IC for an octal number to its binary equivalent Commercial IC available: 74LS148 EI (Enable Input) 0: IC Enable 1: IC Disable EO (Enable Output) = 0 when EI is ‘0’, and no inputs are ‘1’s. GS = 0 when EI is ‘0’, and any of the inputs is ‘1’. Use for expansion

1 The truth table of 74LS148 is given by:

4.6(a) Multiplexer (MUX) (BM: Pemultipleks) Also known as data selector Block diagram of MUX

Basic 4 Input MUX 4 input MUX  2-bit select input (S1 & S0)

74LS151: 8-to-1 MUX INPUT OUTPUT 8 input lines for data 3 high SELECT inputs (as there are 8 input lines) EN input for expanding purposes OUTPUT 2 output lines (Z and Z’)

16-to1 MUX using 74LS151 ICs Two units of 74LS151 (8-to-1) IC can be used to form 16-to-1 MUX.

Generate Logic Function Using 74LS151 Example: Use an 8-to-1 MUX to implement this function, F = ABC’ + A’BC + ABC

4.6(b) Demultiplexer (DEMUX) Operation: reverse of MUX (i.e. data are channelled to one of the output lines depending on SELECT input) Block diagram of DEMUX

74LS138: 1-to-8 DEMUX SELECTOR OUTPUT DATA IN

4.7 Comparator Use to compare two binary numbers. Simplest comparator  detect the equality Complex comparator  detect equality and size Simple Comparator XOR gate is used to detect equality

2-bit Magnitude Comparator It compares two 2-bit binary inputs , A (i.e. A1 & A0) with B (i.e. B1 & B0) .

Therefore, the truth table of 2-bit magnitude comparator is

By simplifying the expressions, For expression M: use Boolean theorem to simplify it. For expression N: use K-map

The combinational logic circuit of this comparator:

4-bit Magnitude Comparator

4.8 Code Converter Contains combinational logic gates to convert one code to another Several types of code converters: BCD-to-binary converter Binary-to-Gray code converter Gray code-to-binary converter

BCD-to-binary conversion The value of each bit in the BCD number is represented by a binary number Tens digit Units digit

BCD-to-binary conversion (cont.) Then, the binary numbers representing the weights of the BCD bits are summed to produce the total binary number.

BCD-to-binary conversion (cont.) Implement this converter by using ADDER circuits

Binary-to-Gray code Converter

Gray code-to-Binary converter

4.9 Parity Bit Generator and Checker Parity bits are determined by the numbers of 1’s in the code. Basic principle: Sum of an even number of 1s = 0 Sum of an odd number of 1s = 1

Parity Generator Even parity generator

Parity Generator Odd parity generator

Parity Checker Even parity checker

Parity Checker Odd parity checker

Summary By combining several logic gates together, we would be able to perform special functions, e.g. HA, FA, MUX, etc