Peripheral IP blocks per chip “Superstrip”

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Presentation transcript:

Peripheral IP blocks per chip “Superstrip” DC-DC converter (?), LDO (low drop-out) voltage regulator, voltage references (bandgap), DACs, control registers (SEU tolerant), temperature sensor, PLL, I/O pads, LVDS transceiver, test signal injection,… Any other suggestion from analog and digital designers? There isn’t yet a maintained repository of these IP blocks (some work in progress in AIDA WP3.3, but it will take time) The CERN MPW service (IBM 130 nm) will put external users in contact with CERN designers; they will provide a list of blocks with contact names We have to decide which blocks we need (also on the basis of system aspects: power and clock distribution)