Digital Design Lecture 9

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Presentation transcript:

Digital Design Lecture 9 Sequential Logic

A General Sequential Circuit

Synchronous Sequential Circuits

Set/Reset Latch (NORs)

Set/Reset Latch (NANDs)

SR Latch with Control

D Latch

Latch Symbols

Clock Response

Master-Slave D Flip-Flop

D-Type Positive-Edge Triggered Flip-Flop

Edge-Triggered D Flip-Flop Graphic Symbol

JK Flip-Flop

Flip-Flop Characteristic Tables D 0 1 Q(t+1) 0 - Reset 1 - Set D – Flip-Flop T 0 1 Q(t+1) Q(t) – No change Q(t) - Complement T – Flip-Flop K 0 1 0 1 J 0 0 1 1 Q(t+1) Q(t) – No change 0 – Reset 1 – Set Q(t) – Complement JK – Flip-Flop Table 5.1

T Flip-Flop

D Flip-Flop with Reset

Sequential Circuit Analysis

State Diagrams

Sequential Circuit: D Flip-Flop

Sequential Circuit: JK Flip-Flop

State Diagram for JK Circuit

Sequential Circuit: T Flip-Flop

Mealy and Moore Models Finite State Machines Output is a function of both the present state and the present input See Figure 5-15 (Slide 16: Sequential Analysis) Moore Output is only a function of the current state See Figure 5-18 (Slide 19: JK Flip-Flop)