Systems Architecture I September 4, 1997 Systems Architecture I (CS 281-001) Lecture 15: A Multicycle Implementation of MIPS* Jeremy R. Johnson Mon. Nov. 22, 1999 *This lecture was derived from material in the text (sec. 5.4-5.5). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). Nov. 22, 1999 Systems Architecture I

Systems Architecture I September 4, 1997 Introduction Objective: To re-implement the MIPS instruction set using a multicycle implementation. The benefits are shared hardware and that instructions can take a different number of cycles (reduced computing time). How: break instructions into steps, each step taking a clock cycle. What’s New: control depends on step Need to store temporary values in internal registers Topics Steps in multicycle implementation Control using finite state machine Control using microprogramming Nov. 22, 1999 Systems Architecture I

Systems Architecture I Multicycle Approach Break up the instructions into steps, each step takes a cycle balance the amount of work to be done restrict each cycle to use only one major functional unit Functional units: memory, register file, and ALU At the end of a cycle Use internal registers to store results between steps Nov. 22, 1999 Systems Architecture I

Systems Architecture I Execution Steps Instruction fetch IR = Memory[PC]; PC = PC + 4; Instruction decode and register fetch A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend (IR[15-0]) << 2); Nov. 22, 1999 Systems Architecture I

Systems Architecture I Execution Steps Execution, memory address computation, or branch completion Memory reference ALUOut = A + sign-extend (IR[15-0]); Arithmetic-logical instruction (R-type) ALUOut = A op B; Branch if (A == B) PC = ALUOut; Jump PC = PC [31-28] || (IR[25-0]<<2) Nov. 22, 1999 Systems Architecture I

Systems Architecture I Execution Steps Memory access or R-type instruction completion memory reference MDR = Memory [ALUOut]; or Memory [ALUOut] = B; R-type completion Reg [IR[15-11]] = ALUOut; Memory read completion Reg [IR[20-16]] = MDR; Nov. 22, 1999 Systems Architecture I

Systems Architecture I Summary 3 - 5 clock cycles Uses “optimistic” actions Nov. 22, 1999 Systems Architecture I

Systems Architecture I CPI in a Multicycle CPU Using the previous multicycle implementation determine the average cycles per instruction (from gcc) 22% loads 11% stores 49% R-format 16% branches 2% jumps CPI = 0.22  5 + 0.11  4 + 0.49  4 + 0.16  3 + 0.02  3 = 4.04 Nov. 22, 1999 Systems Architecture I

Systems Architecture I Control Signals 1-bit control signals RegDst RegWrite ALUSrcA MemRead MemtoReg IorD IRWrite PCWrite PCWriteCond 2-bit control signals ALUOp 00 (add) 01 (sub) 10 (funct field) ALUSrcB 00 (B register) 01 (constant 4) 10 (lower 16 bits from IR) 11 (lower 16 bits from IR shifted left 2 bits) PCSource 00 (output of ALU = PC+4) 01 (ALUOut = branch addr) 10 (jump target) Nov. 22, 1999 Systems Architecture I

Systems Architecture I Complete Datapath Nov. 22, 1999 Systems Architecture I

Systems Architecture I Finite State Machine Set of states Next function determined by input and current state Output determined by current state and possibly input Moore machine (output determined only by current state) Nov. 22, 1999 Systems Architecture I

Systems Architecture I Control Using FSM Nov. 22, 1999 Systems Architecture I

Systems Architecture I Implementation of FSM Nov. 22, 1999 Systems Architecture I

Control using Microprogramming Represent asserted values on control lines symbollically (microinstructions) Fields: Label, ALU control, SRC1, SRC2, Register control, Memory, PCWrite control, Sequencing specifies non-overlapping set of control signals Placed in ROM or PLA (provides address for microinstructions) Sequencing mechanism next microinstruction branch to microinstruction (FETCH) for next MIPS instruction choose next microinstruction based on control unit input (dispatch). Implemented using a table of addresses (dispatch table). Nov. 22, 1999 Systems Architecture I

Microinstruction Fields Nov. 22, 1999 Systems Architecture I

Systems Architecture I Microprogram Nov. 22, 1999 Systems Architecture I

Systems Architecture I Implementation Nov. 22, 1999 Systems Architecture I