CoBo - Different Boundaries & Different Options of Nathan Usher Michigan State University GET Workshop March 10-12, 2009

CoBo Tasks Multiplicity Data Readout and Compression Slow Control Clock Distribution Power and Monitoring

Multiplicity 4x 12-bit trigger sum sent from AsAds Sliding window implemented in CoBo logic AsAd sends instantaneous multiplicity value to CoBo CoBo integrates all multiplicity values in a configurable-length window 11-bit multiplicity output to MUTANT

Sliding Window Example Sum of trigger sum inputs from AsAds 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Sliding window size Multiplicity output to MUTANT 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Sliding window size

Data Compression Zero suppression will be implemented Zero suppression alone will not compress data enough for worst case data rate into CoBo 25 MS/s readout of ASICs is 4.8 Gb/s raw data 12.8 Gb/s if bits for pad and time bucket bits are added Assume Gbit Ethernet can sustain 500 Mb/s average Need to compress to 10.4% (3.9%) Peak finding algorithm? Lossless compression - Zip?

Data Flow Diagram Multiplicity Sliding Window To MUTANT Build event packet and additional compression AsAd multiplicity / trigger PowerPC Core Data Out Data compression pipeline (Runs @ 400 MHz) Buffer 16x12 bits @ 25 MHz DDR2 SDRAM Buffer DDR2 SDRAM Buffer

Slow Control Slow control commands arrive via Ethernet link Commands intended for AsAd are forwarded via SPI link (3.3V signal level) SCLK - serial clock MOSI - command / data to AsAd MISO - response from AsAd SSx - Slave select for each device on AsAds CoBo setup Debug

Clock Distribution SCA write clock - LMK01020 8 LVPECL outputs <30 fs additive jitter (100 Hz to 20 MHz) <80 fs additive jitter at 200 MHz SCA read / ADC clock - LMK02000 PLL clock cleaner Clock distribution 5 LVPECL outputs 3 LVDS outputs <20 fs additive jitter on 100 MHz clock <75 fs additive jitter on divided clocks Synchronization input

CoBo Clock Synchronization 100MHz 25MHz CoBo 1 25MHz Cobo 2 25MHz Cobo 3 Sync

Power and Monitoring CoBo requires 1.0V, 2.5V, and 3.3V supplies Three LDO regulators will be used Voltage and Current monitoring (for each supply) and temperature monitoring Use ADT7519 (same as AsAd) or similar device

CoBo Hardware Single-wide NIM module Based on Xilinx Virtex-5 FX70T 10 CoBo and 1 MUTANT in each crate 1 Ethernet switch with 10 Gb/s uplink needed per crate Based on Xilinx Virtex-5 FX70T 71,680 logic cells, 1 PowerPC core Pin compatible with FX100T 102,400 logic cells, 2 PowerPC cores

Hardware Design Options Buffer memory Dual-port memory Double Buffer Separate data and slow control Ethernet links or use a single link Separate FPGAs for data and slow control or use single FPGA 1 dedicated to slow control / debug Reuse firmware and software from another detector 1 dedicated to data compression / transmission

Buffer Memory Dual-Port SRAM DDR2 SDRAM IDT70T3509MS133BPG 4 needed to achieve required data transfer rate Enough space to buffer six worst case events Approximately $300 each: $1,200 per CoBo DDR2 SDRAM MT47H16M16BG-3:B TR 4 needed to achieve required data rate Must be implemented as a double buffer 2 Chips per buffer half Enough space to buffer 28 worst case events Approximately $10 each: $40 per CoBo

Option 1 RS-232 (Debug / Supervision) 100 Mbit Ethernet Ethernet Jack Slow control Spartan-3 or Virtex-4 FPGA Configuration Memory Gbit Ethernet Ethernet Jack Slow control Data Slow control Virtex 5-FXT XC5VFX70T- 1FFG1136C with embedded PowerPC core FPGA Configuration Memory Xilinx Compact Flash XCF128X Multiplicity 2x ITT-Cannon MDSM-30PE- Z10-VR22 To MUTANT Time stamp / trigger Clock buffers Clocks Clocks SCA read/write control Data Buffer 0 DDR2 SDRAM 512 Mb (16M x 32) 2x MT47H16M16BG-3 Data Buffer 1 DDR2 SDRAM 512 Mb (16M x 32) 2x MT47H16M16BG-3 Samtec QSE-DP-EM series Multiplicity / Data To AsAd LVDS Buffers DS15BR400 Voltage Regulator Voltage Regulator Voltage Regulator

Option 1 Pros Cons Reuse software from another system: EXOGAM II Easiest solution to design firmware and debug Cons Added cost per board Approximately $250 per CoBo if Virtex-4 is used for slow control Approximately $25 per CoBo if Spartan-3 with MicroBlaze can be used Additional Ethernet switches may be required for slow control 100 Mb/s is used for slow control, so cost of additional switches is small (approximately $3 per CoBo)

Option 2 Ethernet Jack Data / Slow control Virtex 4-FX RS-232 (Debug / Supervision) Gbit Ethernet FPGA Configuration Memory Slow control Data Slow control Virtex 5-FXT XC5VFX70T- 1FFG1136C with embedded PowerPC core FPGA Configuration Memory Xilinx Compact Flash XCF128X Multiplicity 2x ITT-Cannon MDSM-30PE- Z10-VR22 To MUTANT Time stamp / trigger Clock buffers Clocks Clocks SCA read/write control Data Buffer 0 DDR2 SDRAM 512 Mb (16M x 32) 2x MT47H16M16BG-3 Data Buffer 1 DDR2 SDRAM 512 Mb (16M x 32) 2x MT47H16M16BG-3 Samtec QSE-DP-EM series Multiplicity / Data To AsAd LVDS Buffers DS15BR400 Voltage Regulator Voltage Regulator Voltage Regulator

Option 2 Pros Reuse much of the slow control firmware and software from another project (EXOGAM II) Easiest programming and debug of data processing FPGA Cons Added cost per board Approximately $250 per Cobo if Virtex-4 is used for slow control High-speed data link between FPGAs could be problematic Probably more difficult to design than just using a single Virtex-5 FPGA

Option 3 RS-232 (Debug / Supervision) Gbit Ethernet Ethernet Jack Data and Slow control Slow control Virtex 5-FXT XC5VFX70T- 1FFG1136C with embedded PowerPC core FPGA Configuration Memory Xilinx Compact Flash XCF128X Multiplicity 2x ITT-Cannon MDSM-30PE- Z10-VR22 To MUTANT Time stamp / trigger Clock buffers Clocks Clocks SCA read/write control Data Buffer 0 DDR2 SDRAM 512 Mb (16M x 32) 2x MT47H16M16BG-3 Data Buffer 1 DDR2 SDRAM 512 Mb (16M x 32) 2x MT47H16M16BG-3 Samtec QSE-DP-EM series Multiplicity / Data To AsAd LVDS Buffers DS15BR400 Voltage Regulator Voltage Regulator Voltage Regulator

Option 3 Pros Slow control code from another project can probably be ported to Virtex-5 relatively easily Firmware can be tested on development board, since only one FPGA is used Easiest board design Minimizes high-speed traces on CoBo circuit board Least expensive parts cost Cons Probably harder to debug than Option 1, but can be mitigated by beginning firmware testing early on development kit Most complex firmware of the three options