EWLP 309-pin by Casio Micronics – Fujitsu

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EWLP 309-pin by Casio Micronics – Fujitsu The largest Full Wafer Level Chip Scale Package Reverse costing analysis by System Plus Consulting Reverse Analysis Report of the largest size Fan-In Wafer Level Package, featuring 309 pins with a pitch of 0.4mm ! System Plus Consulting is proud to publish the reverse costing report of one of the latest Wafer Level Chip Scale Package based on Casio Micronics’ EWLP technology and used by Fujitsu for device MB39C311A, a Power Management Unit + Audio Interface Unit IC for mobile phone. EWLP is an advanced technology for WL-CSP. All the packaging operations are done at the wafer level. The ball pitch is only 0.4mm and only one redistribution layer is used for the 309 balls of this 7.45x7.45 mm package. This WL-CSP is manufactured on 200mm wafers by Casio Micronics. This report provides a complete teardown of the Casio Micronics/Fujitsu 0.4mm pitch WL-CSP package including: Detailed photos Material analysis Manufacturing Process Flow In-depth economical analysis Manufacturing cost breakdown Selling price estimation TABLE OF CONTENTS Overview / Introduction Executive Summary Reverse Costing Methodology Fan-In package Principle Benefits of WL-CSP WL-CSP – Process Flow Physical Analysis Physical Analysis Methodology Mobile Phone & PCB MB39C311A circuit Underfill Die in the package Pads and the redistribution layer Aluminum pad Coupling layer Die metallization and passivation Bumping process Copper posts Summary of Physical Data p4 p7 p12 Manufacturing Process Flow The Process flow main steps WL-CSP Process Flow Redistribution and copper post Bumping and Dicing Cost Analysis Assumptions Package Yields WL-CSP Wafer Cost Wafer Cost by Equipment Family Wafer Cost by Consumable Family WL-CSP Package Cost Synthesis of the Cost Analysis Estimated Manufacturer Price Analysis Price definitions Manufacturers financial ratios Estimated manufacturer Price Conclusion p28 p35 p45 p49 Distributed by

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