96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output Krzysztof Korcyl – IFJ PAN

ADC AD9212 chip specifications Board functionality ADC tests Agenda ADC AD9212 chip specifications Board functionality oriented for the HADES Shower readout ADC tests Future plans

AD9212 chip

AD9212 chip FEATURES Eight ADCs integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode AD9212 chip

HADES Shower readout scheme

Shower Add-On card Version 2 Houses 3 FPGAs Lattice ECP2M and 12 AD9212 ADCs (96 channels) 2 FPGAs process data from ADCs and forward to 3rd FPGA which exports data through Gbit Ethernet to Event Builder 3 Gbps link for communication with HADES Central Trigger Processor Gb Ethernet output Add-on can operate in one of 3 modes: Data taking Calibration Dynamic thresholds adjustment Shower Add-On card Version 2

HADES Shower AddOn functions Dynamic thresholds adjustment Calibration Data taking    Generates 64 internal triggers and integrates pedestal signal from each detector channel Divides by 64 to get average Adds offset (on 4 LSBs) to make threshold Updates local threshold values Exports new settings to Event Builder Generates internal trigger Injects known charge to odd or even FEE asic channels Transfers data from all channels to Event Builder External triggers Each detector channel is compared with individual threshold. Only data exceeding thresholds are transferred to the Event Builder

ADC readout FPGA ADC chip 8 channels integrator average DDR FIFO 2 Frame clock DDR FIFO 2 data0 10 SerPar data7 sampling pattern ADC clock domain board clock domain threshold

Shower Add-On card Version 1 - test setup Old Add-on card was used for ADC tests The old card contains only one FPGA – hence the ADC tests were carried out with single ADC chip Event data were saved to file through Etrax on TRB board

ADC tests ADC differential nonlinearity were measured with sine waveform DNL at 0,1 LSB level

Data taking mode tests In data taking mode, the board waits for external trigger signal, and passes it to the FEE asics The board controls FEE asic and multiplexes 32 detector channels on FEE output. During 300 ns duration of one detector channel at the FEE output, the ADC takes 6 samples (50 ns cycle) and the board makes average. The average is compared to per-channel threshold and sent as event data when greater than.

Sampling tests ADC samples signal with frequency of 20MHz but the FEE asic switches channels with 300 ns cycle From every channel we have six amplitude samples, We skip two first samles and take average of selected pattern from remaining four (4 single samples, 6 doubles or 1 fourfold) By taking mean value from two or four samples we aim to reduce noise

Gaussian fit parameters Sampling tests One sample Average of two samples sample configuration Gaussian fit parameters Mean [ch] Sigma [ch] One sample 531,5 0,55 Two samples 531,6 0,50 Four samples 531,1 0,72 Average of four samples

Future plans Move to Add-on version 2 Tests with full final setup Tests of dynamic threshold calculations Closer investigation of ADC data sampling tests Send data via Gb Ethernet output