SVT – SuperB Workshop – SLAC 6-9 Oct 2009 SVT-Update R&D work organized to prepare a baseline for TDR with: Layer0 based on hybrid pixels hot issues to match SuperB specs: 50x50 mm2 pitch + fast readout Light pixel module support & cooling Pixel module interfaces (Al Bus & fast links) Layer1-Layer5 similar to BaBar SVT Layout Optimization & Design Continue R&D on thin pixel options MAPS with new cell under test (LAB & beams) Continue MAPS irradiation studies Wait for first 3D MAPS device (now in production) Background studies detector & beam pipe design SVT Mechanics Fast Simulation studies (DGWG & FastSim sessions) Impact of L0 efficiency on TD measurements (N. Neri) dE/dx implemented for SVT (J. Walsh) G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

Plans for Hybrid Pixel (I) Produce & test a prototype front-end chip for high resistivity pixels with 50x50 um2 pitch & fast enough readout (background rate ~ 100 MHz/cm2) - Front-end Chip & Pixel sensor matrix layout almost completed both in production from Oct ‘’09 - FE chip: ST 130 nm process, Sensors: FBK-IRST - Sensor + chip bump-bonding next spring (IZM-Berlin)  Testbeam Sept. 2010. FE chip Layout (32x128) – preliminary Details on the FE chip and pixel sensor Matrix today and tomorrow - SVT I and SVT II parallel sessions. 50 mm Cell Layout Thanks to the effort of all the designers (PV/BG-BO-PI) Fabio Morsani is closing the layout as we speak! G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

Plans for Hybrid Pixel (II) PAD on test chip positioned to allow single chip on carrier test but also production of a multichip pixel module: - 3 chips + pixel sensor matrix + Al bus + support with integrated cooling. Pixel module 2 or more chips + sensor and Al pixel bus. Update on pixel bus & pixel module interfaces – M. Citterio Update on Layer0 support & cooling – F. Bosi G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

Light pixel module support & cooling F.Bosi’s talk Light pixel module support & cooling Light support with integrated cooling needed for pixel module: P=2W/cm2 Carbon Fiber support with microchannel for coolant fluid developed: Total support/cooling thickness = 0.28 % X0 (reduction to 0.2% X0 possible) 12.8 mm Prototypes characterized in the Thermo-fluid-dynamics LAB in Pisa varying the specific input power (1-3W/cm2) Measurements confirmed FEA simulation results: T_meas=30-360C @ P=2W/cm2 Measured Temperature along the module T(FEA)=320C @ P=2W/cm2 G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

SVT – SuperB Workshop – SLAC 6-9 Oct 2009 Other SVT activities July 2009 CERN Testbeam New MAPS testbeam in July 2009 (analysis under way). Tested Devices: Analog MAPS (50x50 um pitch) pre/post irradiation (10 Mrad), New MAPS cell 40x40 um pitch S.Bettarini’s talk on Wed. @ 8:30 (SVT II) apsel3T1 Some progress in Background Simulation Hit rate, Radiation Dose, equivalent fluency plots produced for all SVT layers. Machinery is now in place! - R. Cenci’s talk on Wed. @ 10:30 (SVT III) Different beampipe & L0 configurations studied: Rates in L0 still very high. Need some optimization. Activity on strip layers design (L1-L5) has started in Trieste L. Vitale’s talk on Wed. @ 8:30 (SVT II) UK groups (RAL/QMUL) expressed interest in the SVT R&D for TDR F. Wilson’s talk on Wed. @ 10:30 (SVT III) G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

SVT – SuperB Workshop – SLAC 6-9 Oct 2009 Tech. Board Meeting Perugia - June 2009 SVT Milestones (I) Oct. 2009 Front-end chip (ST) & pixel sensor (FBK) submission - OK Simplified Al pixel bus produced (CERN)  NOV ‘09 Thermal/mechanical characterization of pixel module support (CF with microchannels) - OK SVT internal geometry definition - ongoing Dec. 2009 Definition of HDI and links specification (chip-to-HDI and HDI-to-DAQ) L1-L5 module components specs definition (front-end chip, fanout, sensor) Conceptual design Layer0 support & beam pipe Conceptual design of SVT mechanical support G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

SVT – SuperB Workshop – SLAC 6-9 Oct 2009 Tech. Board Meeting Perugia - June 2009 SVT Milestones (II) Apr. 2010 Results on lab. test of front-end chip for Hybrid Pixel Tests on the full pixel module links (by means of FPGAs+Al-BUS+copper/fiber link) L1-L5 module design TDR SVT chapter assignment  start writing Sept 2010 Beam pipe design SVT + Layer0 support design Beam test of Hybrid pixel chip+sensor (if ready!) TDR final writing G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009

Agenda of the SVT Parallels Tuesday 6 Oct. 16-17:30 Introduction – G. Rizzo Update on MAPS activities & FE4D32x128 chip analog cell - G. Traversi (PV/BG) Hybrid pixel readout chip: FE4D32x128 A. Gabrielli (BO) Wednesday 7 Oct 8:30-10:00 First results on analog MAPS from July CERN Testbeam – S. Bettarini (PI) Update on pixel bus & pixel module interfaces – M. Citterio (MI) Update on Pixel Sensor design – G. Dalla Betta (TN) Strip layer design: first considerations – L. Vitale (TS) Wednesday 7 Oct 10:30-12:00 UK Activities & Plans – F. Wilson (RAL) Layer0 support & SVT Mechanics– F. Bosi (PI) Update on SVT Background evaluation – R. Cenci (PI) G. Rizzo SVT – SuperB Workshop – SLAC 6-9 Oct 2009