Figure 8.1. The general form of a sequential circuit.

Slides:

Advertisements

Similar presentations

FSM and Efficient Synthesizable FSM Design using Verilog

Advertisements

State-machine structure (Mealy)

Table 7.1 Verilog Operators.

FSM Revisit Synchronous sequential circuit can be drawn like below  These are called FSMs  Super-important in digital circuit design FSM is composed.

Give qualifications of instructors: DAP

CS 151 Digital Systems Design Lecture 37 Register Transfer Level

FSMs 1 Sequential logic implementation  Sequential circuits  primitive sequential elements  combinational logic  Models for representing sequential.

1 COMP541 Sequencing and Control Montek Singh Mar 29, 2007.

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

Algorithmic State Machine (ASM) Charts

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts,

Sequential Logic in Verilog

Figure 7.1. Control of an alarm system. Memory element Alarm Sensor Reset Set OnOff 

CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 8: Synchronous Sequential Circuits Chapter 8.

Figure A flip-flop with an enable input. D Q Q Q R Clock E 0 1.

Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Ders 8: FSM Gerçekleme ve.

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

EEE2243 Digital System Design Chapter 4: Verilog HDL (Sequential) by Muhazam Mustapha, January 2011.

Register Transfer Level & Design with ASM

Finite State Machine (FSM) Nattha Jindapetch December 2008.

Datapath - performs data transfer and processing operations The control unit sends: – Control signals – Control outputs The control unit receives: – External.

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.

Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Chapter 11: System Design.

EMT 351/4 DIGITAL IC DESIGN Verilog Behavioral Modeling  Finite State Machine -Moore & Mealy Machine -State Encoding Techniques.

Pusat Pengajian Kejuruteraan Mikroelektronik EMT 351/4 DIGITAL IC DESIGN Verilog Behavioural Modeling (Part 4) Week #

1 Lecture 3: Modeling Sequential Logic in Verilog HDL.

Figure Implementation of an FSM in a CPLD..

Overview Logistics Last lecture Today HW5 due today

Partitioning of a digital system.

Supplement on Verilog for Algorithm State Machine Chart

© Copyright 2004, Gaetano Borriello and Randy H. Katz

Supplement on Verilog Sequential circuit examples: FSM

Learning Outcome By the end of this chapter, students are expected to be able to: Design State Machine Write Verilog State Machine by Boolean Algebra and.

FIGURE 5.1 Block diagram of sequential circuit

Digital Principles and Design Algorithmic State Machines

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Recap D flip-flop based counter Flip-flop transition table

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

CSE 370 – Winter Sequential Logic-2 - 1

Instructor: Alexander Stoytchev

FSM MODELING MOORE FSM MELAY FSM. Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-2]

VHDL (VHSIC Hardware Description Language)

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

COE 202 Introduction to Verilog

Instructor: Alexander Stoytchev

Supplement on Verilog Sequential circuit examples: FSM

Register-Transfer Level Components in Verilog

Figure 8.1. The general form of a sequential circuit.

KU College of Engineering Elec 204: Digital Systems Design

Dr. Tassadaq Hussain Introduction to Verilog – Part-3 Expressing Sequential Circuits and FSM.

ASM and Micro-programmed State Machines

Instructor: Alexander Stoytchev

The Verilog Hardware Description Language

Instructor: Alexander Stoytchev

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code.

Guest Lecture by David Johnston

Lecture 4: Continuation of SystemVerilog

ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL code ECE 448 – FPGA and ASIC Design.

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Dr. Tassadaq Hussain Introduction to Verilog – Part-4 Expressing FSM in Verilog (contd) and FSM State Encoding Dr. Tassadaq Hussain.

Instructor: Alexander Stoytchev

CSE 370 – Winter Sequential Logic-2 - 1

Presentation transcript:

Figure 8.1. The general form of a sequential circuit. W Combinational Combinational Flip-flops Z circuit circuit Q Clock Figure 8.1. The general form of a sequential circuit.

Figure 8.2. Sequences of input and output signals. Clockcycle: t t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 w : 1 1 1 1 1 1 1 z : 1 1 1 Figure 8.2. Sequences of input and output signals.

Figure 8.3. State diagram of a simple sequential circuit. Reset w = 1 w = A ¤ z = B ¤ z = w = w = w = 1 C ¤ z = 1 w = 1 Figure 8.3. State diagram of a simple sequential circuit.

z w = w = 1 Next state Present Output state A A B B A C C A C 1 w = 1 A A B B A C C A C 1 Figure 8.4. State table.

Figure 8.5. A general sequential circuit. Y y 1 1 w Combinational Combinational z circuit circuit Y y 2 2 Clock Figure 8.5. A general sequential circuit.

Figure 8.6. A state-assigned table. Next state Present Output state w = w = 1 z y y Y Y Y Y 2 1 2 1 2 1 A 00 00 01 B 01 00 10 C 10 00 10 1 11 dd dd d Figure 8.6. A state-assigned table.

Figure 8.7. Derivation of logic expressions. y y 2 1 Ignoring don't cares Using don't cares w 00 01 11 10 d Y = wy y Y = wy y 1 1 2 1 1 2 1 1 d y y 2 1 w 00 01 11 10 d Y = wy y + wy y Y = wy + wy 2 1 2 1 2 2 1 2 1 1 d 1 = w ( y + y ) 1 2 y 1 y 2 1 z = y y z = y 1 2 2 1 1 d Figure 8.7. Derivation of logic expressions.

Figure 8.8. Sequential circuit derived in Figure 8.7.

Figure 8.9. Timing diagram. t t t t t t t t t t t 1 Clock 1 w 1 y 1 y 1 2 3 4 5 6 7 8 9 10 1 Clock 1 w 1 y 1 1 y 2 1 z Figure 8.9. Timing diagram.

Figure 8.10. Signals needed in Example 8.1. out R 1 w in R 2 out Control R 2 circuit in R 3 out Clock R 3 in Done Figure 8.10. Signals needed in Example 8.1.

Figure 8.11. State diagram. ¤ ¤ , ¤ , ¤ , , w = A No transfer Reset w A ¤ No transfer Reset w = 1 B ¤ R 2 = 1 , R 3 = 1 out in w = w = 1 w = w = 1 C ¤ R 1 = 1 , R 2 = 1 out in w = w = 1 D ¤ R 3 = 1 , R 1 = 1 , Done = 1 out in Figure 8.11. State diagram.

Present Next state Outputs state w = 0 w = 1 A A B B C C 1 1 C D D 1 1 D A A 1 1 1 Figure 8.12. State table.

Figure 8.13. State-assigned table.

Figure 8.14. Derivation of next-state expressions.

Figure 8.15. Sequential circuit derived in Figure 8.14.

Present Next state state w = 1 Output y Y z A 00 01 B 11 C 10 dd d 1 Output y 2 Y z A 00 01 B 11 C 10 dd d Figure 8.16. Improved state assignment for the sequential circuit in Figure 8.4.

Figure 8.17. Final circuit for the improved state assignment. Y y 2 2 D Q z Q Y y 1 1 w D Q Clock Q Resetn Figure 8.17. Final circuit for the improved state assignment.

Figure 8.18. Improved state assignment for the sequential circuit in Figure 8.12.

Figure 8.19. Derivation of next-state expressions. y y 2 1 w 00 01 11 10 1 Y = wy + y y 1 2 1 2 1 1 1 y y 2 1 w 00 01 11 10 1 1 Y = y 2 1 1 1 1 Figure 8.19. Derivation of next-state expressions.

Present Nextstate state Output w = w = 1 z y y y Y Y Y Y Y Y A 001 001 w = 1 z y y y 3 2 1 Y Y Y Y Y Y 3 2 1 3 2 1 A 001 001 010 B 010 001 100 C 100 001 100 1 Figure 8.20. One-hot state assignment for the sequential circuit in Figure 8.4.

Figure 8.21. One-hot state assignment for the sequential circuit in Figure 8.12.

Figure 8.22. Sequences of input and output signals. Clock cycle: t t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 w : 1 1 1 1 1 1 1 z : 1 1 1 Figure 8.22. Sequences of input and output signals.

Figure 8.23. State diagram. ¤ ¤ ¤ ¤ Reset w = 1 z = w = z = A B w = 1 w = ¤ z = A B w = 1 ¤ z = 1 w = ¤ z = Figure 8.23. State diagram.

Next state Output z Present state w = w = 1 w = w = 1 A A B B A B 1 w = 1 w = w = 1 A A B B A B 1 Figure 8.24. State table.

Figure 8.25. State-assigned table. Next state Output Present state w = w = 1 w = w = 1 y Y Y z z A 1 B 1 1 1 Figure 8.25. State-assigned table.

Figure 8.26. Implementation of FSM in Figure 8.25. z w D Q y Clock Q Resetn (a) Circuit t t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 1 Clock 1 w 1 y 1 z (b) Timing diagram Figure 8.26. Implementation of FSM in Figure 8.25.

Figure 8.27. Circuit that implements the specification in Figure 8.2.

Figure 8.28. State diagram for Example 8.4. w = A Reset w = 1 ¤ R 2 = 1 , R 3 = 1 out in B w = R 1 = 1 , R 2 = 1 w = 1 out in C w = R 3 = 1 , R 1 = 1 , Done = 1 w = 1 out in Figure 8.28. State diagram for Example 8.4.

Figure 8.29. Verilog code for the FSM in Figure 8.3. module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w or y) case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; C: if (w) Y = C; default: Y = 2'bxx; endcase // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) y <= A; else y <= Y; // Define output assign z = (y == C); endmodule Figure 8.29. Verilog code for the FSM in Figure 8.3.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.30. Implementation of an FSM in a CPLD.

Figure 8.31. An FSM circuit in a small CPLD.

Figure 8.32. Simulation results.

Figure 8.33. Second version of code for the FSM in Figure 8.3. module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w or y) begin case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; C: if (w) Y = C; default: Y = 2'bxx; endcase z = (y == C); //Define output end // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) y <= A; else y <= Y; endmodule Figure 8.33. Second version of code for the FSM in Figure 8.3.

Figure 8.34. Third version of code for the FSM in Figure 8.3. module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the sequential block always @(negedge Resetn or posedge Clock) if (Resetn == 0) y <= A; else case (y) A: if (w) y <= B; else y <= A; B: if (w) y <= C; C: if (w) y <= C; default: y <= 2'bxx; endcase // Define output assign z = (y == C); endmodule Figure 8.34. Third version of code for the FSM in Figure 8.3.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.35. Verilog code for the FSM in Figure 8.11.

Figure 8.36. Verilog code for the Mealy machine of Figure 8.23. Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.36. Verilog code for the Mealy machine of Figure 8.23.

Figure 8.37. Simulation results for the Mealy machine.

Figure 8.38. Potential problem with asynchronous inputs to a Mealy FSM.

Figure 8.39. Block diagram of a serial adder. Shift register s Adder FSM Shift register Shift register b Sum = A + B B Clock Figure 8.39. Block diagram of a serial adder.

Figure 8.40. State diagram for the serial adder.

Figure 8.41. State table for the serial adder. Next state Output s Present state ab =00 01 10 11 00 01 10 11 G G G G H 1 1 H G H H H 1 1 Figure 8.41. State table for the serial adder.

Figure 8.42. State-assigned table for the serial adder. Next state Output Present state ab =00 01 10 11 00 01 10 11 y Y s 1 1 1 1 1 1 1 1 1 Figure 8.42. State-assigned table for the serial adder.

Figure 8.43. Circuit for the adder FSM. Full b adder Y y D Q carry-out Clock Q Reset Figure 8.43. Circuit for the adder FSM.

Figure 8.44. State diagram for the Moore-type serial adder FSM. Reset 11 01 00 G ¤ s = H ¤ s = 10 00 01 01 00 11 10 11 10 01 G ¤ s = 1 H ¤ s = 1 11 10 1 00 1 Figure 8.44. State diagram for the Moore-type serial adder FSM.

Figure 8.45. State table for the Moore-type serial adder FSM. Nextstate Present Output state ab =00 01 10 11 s G G G G H 1 1 G G G G H 1 1 1 1 H G H H H 1 1 H G H H H 1 1 1 1 Figure 8.45. State table for the Moore-type serial adder FSM.

Figure 8.46. State-assigned table for the Moore-type serial adder FSM. Nextstate Present Output state ab =00 01 10 11 y y s 2 1 Y Y 2 1 00 01 1 10 01 01 1 10 1 10 1 10 1 11 11 1 10 1 11 1 Figure 8.46. State-assigned table for the Moore-type serial adder FSM.

Figure 8.47. Circuit for the Moore-type serial adder FSM. Sum bit Y y 1 1 a D Q s Full b adder Carry-out Q Y y 2 2 D Q Clock Q Reset Figure 8.47. Circuit for the Moore-type serial adder FSM.

module shiftrne (R, L, E, w, Clock, Q); parameter n = 8; input [n-1:0] R; input L, E, w, Clock; output [n-1:0] Q; reg [n-1:0] Q; integer k; always @(posedge Clock) if (L) Q <= R; else if (E) begin for (k = n-1; k > 0; k = k-1) Q[k-1] <= Q[k]; Q[n-1] <= w; end endmodule Figure 8.48. Code for a left-to-right shift register with an enable input.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.49. Verilog code for the serial adder.

Figure 8.50a. Synthesized serial adder. 1 a a D D D D 7 3 2 1 L E Counter L w Q Q Q Q 3 2 1 1 E Adder b b 7 FSM Run L w 1 E L w E Clock Reset Sum Sum 7 Figure 8.50a. Synthesized serial adder.

Figure 8.50b. Simulation results for the synthesized serial adder.

Figure 8.51. State table for Example 8.6. Next state Present Output state z w = w = 1 A B C 1 B D F 1 C F E D B G 1 E F C F E D G F G Figure 8.51. State table for Example 8.6.

Figure 8.52. Minimized state table for Example 8.6. Nextstate Present Output state z w = w = 1 A B C 1 B A F 1 C F C F C A Figure 8.52. Minimized state table for Example 8.6.

Figure 8.53. Signals for the vending machine. Clock sense N sense D N D (a) Timing diagram N sense N D Q D Q Clock Q Q (b) Circuit that generates N Figure 8.53. Signals for the vending machine.

Figure 8.54. State diagram for Example 8.7. DN Reset DN DN S1 ¤ DN DN DN D N D S4 ¤ 1 S2 ¤ S3 ¤ S7 ¤ 1 N D N DN S5 ¤ 1 S6 ¤ DN DN N D S8 ¤ 1 S9 ¤ 1 Figure 8.54. State diagram for Example 8.7.

Figure 8.55. State table for Example 8.7. Next state Present Output state z DN =00 01 10 11 S1 S1 S3 S2 – S2 S2 S4 S5 – S3 S3 S6 S7 – S4 S1 – – – 1 S5 S3 – – – 1 S6 S6 S8 S9 – S7 S1 – – – 1 S8 S1 – – – 1 S9 S3 – – – 1 Figure 8.55. State table for Example 8.7.

Figure 8.56. Minimized state table for Example 8.7. Next state Present Output state z DN =00 01 10 11 S1 S1 S3 S2 – S2 S2 S4 S5 – S3 S3 S2 S4 – S4 S1 – – – 1 S5 S3 – – – 1 Figure 8.56. Minimized state table for Example 8.7.

Figure 8.57. Minimized state diagram for Example 8.7. DN S1 ¤ N DN S3 ¤ D DN N DN D DN S2 ¤ S5 ¤ 1 N D S4 ¤ 1 Figure 8.57. Minimized state diagram for Example 8.7.

Figure 8.58. Mealy-type FSM for Example 8.7. DN ¤ S1 N ¤ D ¤ 1 DN ¤ N ¤ 1 S3 D ¤ N ¤ D ¤ 1 S2 DN ¤ Figure 8.58. Mealy-type FSM for Example 8.7.

Figure 8.59. Incompletely specified state table for Example 8.8. Next state Output z Present state w = w = 1 w = w = 1 A B C B D – – C F E 1 D B G E F C 1 F E D 1 G F – – Figure 8.59. Incompletely specified state table for Example 8.8.

Figure 8.60. State diagram for a counter. w = w = w = w = w = 1 w = 1 w = 1 A/0 B/1 C/2 D/3 w = 1 w = 1 H/7 G/6 F/5 E/4 w = 1 w = 1 w = 1 w = w = w = w = Figure 8.60. State diagram for a counter.

Figure 8.61. State table for the counter. Next state Present Output state w = w = 1 A A B B B C 1 C C D 2 D D E 3 E E F 4 F F G 5 G G H 6 H H A 7 Figure 8.61. State table for the counter.

Figure 8.62. State-assigned table for the counter. Next state Present Count state w = w = 1 y y y z z z 2 1 2 1 Y Y Y Y Y Y 2 1 2 1 A 000 000 001 000 B 001 001 010 001 C 010 010 011 010 D 011 011 100 011 E 100 100 101 100 F 101 101 110 101 G 110 110 111 110 H 111 111 000 111 Figure 8.62. State-assigned table for the counter.

Figure 8.63. Karnaugh maps for D flip-flops for the counter. y y y y 1 1 wy wy 2 00 01 11 10 2 00 01 11 10 00 1 1 00 1 1 01 1 1 01 1 1 11 1 1 11 1 1 10 1 1 10 1 1 Y = wy + wy Y = wy + y y + wy y 1 1 1 1 y y 1 wy 2 00 01 11 10 00 01 1 1 1 1 11 1 1 1 10 1 Y = wy + y y + y y + w y y y 2 2 2 1 2 1 2 Figure 8.63. Karnaugh maps for D flip-flops for the counter.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.64. Circuit diagram for the counter.

Figure 8.65. Excitation table for the counter with JK flip-flops. Flip-flop inputs Present Count state w = w = 1 y y y z z z 2 1 2 1 Y Y Y J K J K J K Y Y Y J K J K J K 2 1 2 2 1 1 2 1 2 2 1 1 A 000 000 0d 0d 0d 001 0d 0d 1d 000 B 001 001 0d 0d d0 010 0d 1d d1 001 C 010 010 0d d0 0d 011 0d d0 1d 010 D 011 011 0d d0 d0 100 1d d1 d1 011 E 100 100 d0 0d 0d 101 d0 0d 1d 100 F 101 101 d0 0d d0 110 d0 1d d1 101 G 110 110 d0 d0 0d 111 d0 d0 1d 110 H 111 111 d0 d0 d0 000 d1 d1 d1 111 Figure 8.65. Excitation table for the counter with JK flip-flops.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.66. Karnaugh maps for JK flip-flops in the counter.

Figure 8.67. Circuit diagram using JK flip-flops.

Figure 8.68. Factored-form implementation of the counter.

Figure 8.69. State table for the counterlike example. Present Next Output state state z z z 2 1 A B 000 B C 100 C D 010 D E 110 E F 001 F G 101 G H 011 H A 111 Figure 8.69. State table for the counterlike example.

Figure 8.70. State-assigned table. Present Next Output state state y y y Y Y Y z z z 2 1 2 1 2 1 000 1 00 00 100 10 1 00 010 1 10 10 110 01 1 10 001 1 01 01 101 11 1 01 011 1 11 11 111 00 1 11 Figure 8.70. State-assigned table.

Figure 8.71. Circuit for the counterlike example. D Q z 2 Q D Q z 1 Q D Q z w Q Figure 8.71. Circuit for the counterlike example.

Figure 8.72. State diagram for the arbiter. Reset 000 Idle 0xx 1xx gnt1 ¤ g = 1 1 x0x 1xx 01x gnt2 ¤ g = 1 2 xx0 x1x 001 gnt3 ¤ g = 1 3 xx1 Figure 8.72. State diagram for the arbiter.

Figure 8.73. Alternative style of state diagram for the arbiter. Reset 1 2 3 Idle r r 1 1 gnt1 ¤ g = 1 1 r r r r 2 1 1 2 gnt2 ¤ g = 1 2 r r 2 r r r 3 1 2 3 gnt3 ¤ g = 1 3 r 3 Figure 8.73. Alternative style of state diagram for the arbiter.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.74. Verilog code for the arbiter.

Figure 8.75. Simulation results for the arbiter circuit.

Figure 8.76. Output delays in the arbiter circuit.

Figure 8.77. Output delay when using one-hot encoding.

Figure 8.78. Circuit for Example 8.9.

Figure 8.79. Tables for the circuit in Example 8.9. Next State Present Output state w = w = 1 Next state Present Output y y z 2 1 state z Y Y Y Y w = w = 1 2 1 2 1 01 A A B 1 10 B A C 1 11 C A D 1 1 11 1 D A D 1 (a) State-assigned table (b) State table Figure 8.79. Tables for the circuit in Example 8.9.

Figure 8.80. Circuit for Example 8.10. J y 1 1 w J Q z K Q K 1 J y 2 2 J Q Clock K Q K 2 Resetn Figure 8.80. Circuit for Example 8.10.

Figure 8.81. Excitation table for the circuit in Figure 8.80. Flip-flop inputs Present Output state w = w = 1 y y z 2 1 J K J K J K J K 2 2 1 1 2 2 1 1 00 01 1 1 1 01 01 1 1 1 1 10 01 1 1 11 01 1 1 1 1 Figure 8.81. Excitation table for the circuit in Figure 8.80.

Figure 8.82. Circuit for Example 8.11.

Figure 8.83. Excitation table for the circuit in Figure 8.82. Flip-flop inputs Present Output state w = w = 1 y y z 2 1 T D T D 2 1 2 1 01 1 10 1 1 01 1 1 1 01 1 Figure 8.83. Excitation table for the circuit in Figure 8.82.

Figure 8.84. Elements used in ASM charts. State name Output signals 0 (False) 1 (True) Condition or actions expression (Moore type) (a) State box (b) Decision box Conditional outputs or actions (Mealy type) (c) Conditional output box Figure 8.84. Elements used in ASM charts.

Please see “portrait orientation” PowerPoint file for Chapter 8 Figure 8.85. ASM chart for a simple FSM.

Figure 8.86. ASM chart for the FSM in Figure 8.23.

Figure 8.87. ASM chart for the arbiter. Reset Idle 1 r 1 gnt1 1 g 1 r 1 1 r 2 gnt2 1 g 2 r 2 1 r 3 gnt3 1 g 3 r 3 Figure 8.87. ASM chart for the arbiter.

Figure 8.88. The general model for a sequential circuit. w z 1 1 Inputs Outputs w Combinational z n m circuit y k Y k Present-state Next-state variables variables y 1 Y 1 Figure 8.88. The general model for a sequential circuit.

Figure P8.1. State-assigned table for problems 8.1 and 8.2. Present Next state Output state w = w = 1 y y z 2 1 Y Y Y Y 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure P8.1. State-assigned table for problems 8.1 and 8.2.

Figure P8.2. Circuit for problem 8.29.