1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Review for the Final Exam
CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff The FINAL exam is scheduled for
Wednesday Dec. 7:30-9:30 AM
That is 7:30 AM 
It will be in this room.

4. Administrative Stuff Please check your grades on BlackBoard
Let me know if something is wrong or missing

5. Final Exam Format The exam will cover: Chapter 1 to Chapter 6
Emphasis will be on Chapter 6 and Chapter 5
The exam will be open book and open notes (you can bring up to 5 pages of handwritten notes) plus your textbook.

6. Final Exam Format The exam will be out of 130 points
You need 95 points to get an A
It will be great if you can score more than 100 points.
but you can’t roll over your extra points 

7. Topics for the Final Exam
K-maps for 2, 3, and 4 variables
Multiplexers (circuits and function)
Synthesis of logic functions using multiplexers
Shannon’s Expansion Theorem
1’s complement and 2’s complement representation
Addition and subtraction of binary numbers
Circuits for adding and subtracting
Serial adder
Latches (circuits, behavior, timing diagrams)
Flip-Flops (circuits, behavior, timing diagrams)
Counters
Registers

8. Topics for the Final Exam
Synchronous Sequential Circuits
FSMs
Moore Machine
Mealy Machines
State diagrams, state tables, state-assigned tables
State minimization
Designing a counter
Arbiter Circuits
Reverse engineering a circuit
ASM Charts
Register Machines
Something from Star Wars

9. How to Study for the Final Exam
Form a study group
Go over the slides for this class
Go over the problems at the end of Ch 5 & 6
Exercise
Get some sleep

10. Sample Problems

11. ASM Charts Given an ASM chart draw the corresponding FSM

12. ASM Charts Given an ASM chart draw the corresponding FSMz 1 =
Reset B A w
[ Figure 6.82 from the textbook ]
[ Figure 6.3 from the textbook ]

14. ASM Charts Given an FSM draw the corresponding ASM Chart

15. ASM Charts Given an FSM draw the corresponding ASM Chart
[ Figure 6.23 from the textbook ]
[ Figure 6.83 from the textbook ]

17. Circuit Implantation of FSMs Implement this state-assigned Table using JK flip-flips

18. Circuit Implantation of FSMs Implement this state-assigned Table using JK flip-flips

19. Excitation table with JK flip-flops
Circuit Implantation of FSMs Implement this state-assigned Table using JK flip-flips
Excitation table with JK flip-flops
[ Figure 6.94 from the textbook ]

21. Register Machines: What does this program do?
How many balls are left in each register at the end of the program?
Register 1
Register 2
Register 3
STEP
INSTRUCTION
REGISTER
GO TO STEP
[BRANCH TO STEP] 1.
Deb 3 1 2 2. 4 3.
Inc 4.
End

22. Move the contents of register 2 to register 3
Register Machines:
Move the contents of register 2 to register 3
Register 1
Register 2
Register 3
STEP
INSTRUCTION
REGISTER
GO TO STEP
[BRANCH TO STEP] 1.
Deb 3 1 2 2. 4 3.
Inc 4.
End

24. Register Machines: What does this program do?
How many balls are left in each register at the end of the program?
Register 1
Register 2
Register 3
STEP
INSTRUCTION
REGISTER
GO TO STEP
[BRANCH TO STEP] 1.
Deb 3 1 2 2. 3. 4 6 4.
Inc 5 5. 6. 7 8 7. 8.
End

25. Register Machines: Copy the contents of register 1 to register 3
using register 2 as a temporary storage
Register 1
Register 2
Register 3
STEP
INSTRUCTION
REGISTER
GO TO STEP
[BRANCH TO STEP] 1.
Deb 3 1 2 2. 3. 4 6 4.
Inc 5 5. 6. 7 8 7. 8.
End

27. What does this circuit do?
[ Figure 6.75 from the textbook ]

28. Approach Find the flip-flops
Outputs of the flip-flops = present state variables
Inputs of the flip-flops determine the next state variables
Determine the logical expressions for the outputs
Given this info it is easy to do the state-assigned table
Next do the state table
Finally, draw the state diagram.

29. Goal
Given a circuit diagram for a synchronous sequential circuit, the goal is to figure out the FSM
Figure out the present state variables, the next state variables, the state-assigned table, the state table, and finally the state diagram.
In other words, the goal is to reverse engineer the circuit.

30. What does this circuit do?
[ Figure 6.75 from the textbook ]

31. Approach Find the flip-flops
Outputs of the flip-flops = present state variables
Inputs of the flip-flops determine the next state variables
Determine the logical expressions for the outputs
Given this info it is easy to do the state-assigned table
Next do the state table
Finally, draw the state diagram.

32. Where are the inputs?
[ Figure 6.75 from the textbook ]

33. Where are the inputs? There is only one input
[ Figure 6.75 from the textbook ]

34. Where are the outputs?
[ Figure 6.75 from the textbook ]

35. Where are the outputs? There is only one output
[ Figure 6.75 from the textbook ]

36. Where kind of machine is this?
Moore or Mealy?
output
input

37. Moore: because the output does not depend directly on the primary input

38. Where are the memory elements?

39. Where are the memory elements?

40. Where are the outputs of the flip-flops?

41. Where are the outputs of the flip-flops?

42. These are the present-state variables

43. Where are the inputs of the flip-flops?

44. Where are the inputs of the flip-flops?

45. These are the next-state variables

46. What are their logic expressions?

47. What are their logic expressions?
Y1 = wy1 + wy2
Y2 = wy1 + wy2

48. Where is the output, again?

49. Where is the output, again?

50. What is its logic expression?

51. What is its logic expression?
z = y1y2

52. This is what we have to work with now
(we don’t need the circuit anymore)
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

53. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

54. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

55. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

56. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

57. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

58. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

59. Let’s derive the state-assigned table
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

60. We don’t need the logic expressions anymore
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
Y1 = wy1 + wy2
Y2 = wy1 + wy2
z = y1y2

61. We don’t need the logic expressions anymore
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1

62. Let’s derive the state table
Present
Next state
Output
state w = 1 z
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

63. Let’s derive the state table
Present
Next state
Output
state w = 1 z
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

64. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

65. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

66. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

67. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

68. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

69. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table

70. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table
The output is the same in both tables

71. The two tables for the initial circuit
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table
[ Figure 6.76 from the textbook ]

72. We don’t need the state-assigned table anymore
Present
Next state
Output
state w = 1 z A B C D
Present
Next State
state w = 1
Output y 2 Y z
0 1
1 0
1 1
State table
State-assigned table
[ Figure 6.76 from the textbook ]

73. We don’t need the state-assigned table anymore
Present
Next state
Output
state w = 1 z A B C D
State table

74. Let’s Draw the State Diagram
Present
Next state
Output
state w = 1 z A B C D

75. Let’s Draw the State Diagram
B / 0
C / 0
D / 1
Present
Next state
Output
state w = 1 z A B C D
Because this is a Moore machine
the output is tied to the state

76. Let’s Draw the State Diagram
B / 0
C / 0
D / 1
Present
Next state
Output
state w = 1 z A B C D
All transitions when the input w is equal to 1

77. Let’s Draw the State Diagram
B / 0
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
All transitions when the input w is equal to 1

78. Let’s Draw the State Diagram
B / 0
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
All transitions when the input w is equal to 0

79. Let’s Draw the State Diagram
B / 0
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
All transitions when the input w is equal to 0

80. We are done! w=0 w=1 w = 1 z Present Next state Output state A B C D1 z A B C D
State table
State diagram

81. Almost done. What does this FSM do?
B / 0
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
State table
State diagram

82. Almost done. What does this FSM do?
It sets the output z to 1 when
three consecutive 1’s occur on the input w.
In other words, it is a sequence detector
for the input pattern 111.
A / 0
w=0
B / 0
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
State table
State diagram

83. Another Example
(with JK flip-flops)

84. What does this circuit do?J Q
Clock
Resetn y 2 1 w z K
[ Figure 6.77 from the textbook ]

85. Approach Find the flip-flops
Outputs of the flip-flops = present state variables
Inputs of the flip-flops determine the next state variables
Determine the logical expressions for the outputs
Given this info it is easy to do the state-assigned table
Next do the state table
Finally, draw the state diagram.

86. Where are the inputs and outputs?J Q
Clock
Resetn y 2 1 w z K
[ Figure 6.77 from the textbook ]

87. Where are the inputs and outputs?J Q
Clock
Resetn y 2 1 w z K
input
output

88. What kind of machine is this?J Q
Clock
Resetn y 2 1 w z K
input
output

89. Where are the flip-flops?J Q
Clock
Resetn y 2 1 w z K

90. Where are the flip-flops?J Q
Clock
Resetn y 2 1 w z K

91. Where are the outputs of the flip-flops?J Q
Clock
Resetn y 2 1 w z K

92. Where are the outputs of the flip-flops?J Q
Clock
Resetn y 2 1 w z K

93. These are the next-state variablesJ Q
Clock
Resetn y 2 1 w z K

94. Where are the inputs of the flip-flops?J Q
Clock
Resetn y 2 1 w z K

95. Where are the inputs of the flip-flops?J Q
Clock
Resetn y 2 1 w z K

96. What are their logic expressions?J Q
Clock
Resetn y 2 1 w z K

97. What are their logic expressions?
J1 = w J Q
Clock
Resetn y 2 1 w z K
K1 = w + y2
J2 = w y1
K2 = w

98. What is the logic expression of the output?J Q
Clock
Resetn y 2 1 w z K
output

99. What is the logic expression of the output?
z = y1y2 J Q
Clock
Resetn y 2 1 w z K
output

100. This is what we have to work with now
(we don’t need the circuit anymore)
J1 = w
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

101. Let’s derive the excitation table
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

102. Let’s derive the excitation table
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

103. Let’s derive the excitation table
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

104. Let’s derive the excitation table
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

105. Let’s derive the excitation table
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

106. Let’s derive the excitation table
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2

107. The excitation table J1 = w K1 = w + y2 J2 = w y1 K2 = w z = y1y2
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2
[ Figure 6.78 from the textbook ]

108. We don’t need the logic expressions anymore
J1 = w
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
K1 = w + y2
J2 = w y1
K2 = w
z = y1y2
[ Figure 6.78 from the textbook ]

109. We don’t need the logic expressions anymore
Present
Flip-flop inputs
state w = 1
Output y 2 J K z 00 01 10 11
[ Figure 6.78 from the textbook ]

110. Let’s derive the state table
Present
Next state
Output
state w = 1 z
State table
Excitation table

111. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
State table
Excitation table
This step is easy
(map 2-bit numbers to 4 letters)

112. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D
State table
Excitation table
This step is easy too
(the outputs are the same in both tables)

113. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D ?
State table
Excitation table
How should we do this?

114. JK Flip-Flop Refresher
D = JQ + KQ
[ Figure 5.16a from the textbook ]

115. JK Flip-Flop RefresherQ K 1 t + ( )
(b) Truth table
(c) Graphical symbol D
Clock
(a) Circuit
[ Figure 5.16 from the textbook ]

116. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D ?
State table
Excitation table
How should we do this?

117. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D

118. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D

119. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A
Note that A = 00

120. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A ?

121. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A

122. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A

123. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A

124. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A
= 1 = 0

125. Let’s derive the state table
Present
Next state
Output
state w = 1 z A B C D A C
Note that C = 10 =0

126. The two tables for the initial circuit
Present
Next state
Output
state w = 1 z A B C D
State table
Excitation table

127. The state diagram w=0 w=1 w = 1 z Present Next state Output state A B
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
State table
State diagram

128. The state diagram Thus, this FSM is identical to the one
w=0
B / 0
C / 0
D / 1
w=1
Thus, this FSM is identical to the one
in the previous example, even though
the circuit uses JK flip-flops.
Present
Next state
Output
state w = 1 z A B C D
State table
State diagram

129. (with mixed flip-flops)
Yet Another Example
(with mixed flip-flops)

130. What does this circuit do?
[ Figure 6.79 from the textbook ]

131. Approach Find the flip-flops
Outputs of the flip-flops = present state variables
Inputs of the flip-flops determine the next state variables
Determine the logical expressions for the outputs
Given this info it is easy to do the state-assigned table
Next do the state table
Finally, draw the state diagram.

132. What are the logic expressions?
[ Figure 6.79 from the textbook ]

133. What are the logic expressions?

134. What are the logic expressions?
D1 = w (y1 + y2)
z = y1y2
T2 = w y2 + w y1y2

135. The Excitation Table D1 = w (y1 + y2) T2 = w y2 + w y1y2 z = y1y2
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
D1 = w (y1 + y2)
T2 = w y2 + w y1y2
z = y1y2
Excitation table

136. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z

137. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D
This step is easy
(map 2-bit numbers to 4 letters)

138. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1
This step is easy too
(the outputs are the same in both tables)

139. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z ? A B C D 1
What should we do here?

140. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z ? A B C D 1
What should we do here?

141. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1

142. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1

143. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1

144. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1

145. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1

146. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D 1

147. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1
Note that A = 00

148. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C ? D 1
What should we do here?

149. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1

150. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1

151. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1

152. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1 1

153. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1 1

154. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D 1 1

155. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A A B C D D 1
Note that D = 11 1

156. Let’s derive the state table
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D

157. The two tables for the initial circuit
Present
Flip-flop inputs
state w = 1
Output y 2 T D z 01 10
Present
Next state
Output
state w = 1 z A B C D
State table
Excitation table
[ Figure 6.75b from the textbook ]
[ Figure 6.80 from the textbook ]

158. The state diagram w=0 w=1 w = 1 z Present Next state Output state A B
C / 0
D / 1
w=1
Present
Next state
Output
state w = 1 z A B C D
State table
State diagram

159. The state diagram Thus, this FSM is identical to the ones
w=0
B / 0
C / 0
D / 1
w=1
Thus, this FSM is identical to the ones
in the previous examples, even though
the circuit uses JK flip-flops.
Present
Next state
Output
state w = 1 z A B C D
State table
State diagram

161. State Minimization

162. State Table for This Example
Next state
Present
Output
state z w = w = 1 A B C 1 B D F 1 C F E D B G 1 E F C F E D G F G
[ Figure 6.51 from the textbook ]

163. State Diagram
(just the states) B C E A G D F

164. State Diagram
(transitions when w=0) B C E A G D F

165. State Diagram
(transitions when w=1) B C E A G D F

166. Outputs B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

167. (All states in the same partition)B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

168. Partition #1
(ABCDEFG) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

169. Partition #2 (based on outputs) B C E A G D F z=1 z=0 z=0 z=1 z=0 z=1

170. Partition #2 (ABD)(CEFG) B C E A G D F z=1 z=0 z=0 z=1 z=0 z=1 z=0 z=1

171. (Examine the 0-successors of ABD)
Partition #3.1
(Examine the 0-successors of ABD) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

172. (Examine the 1-successors of ABD)
Partition #3.1
(Examine the 1-successors of ABD) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

173. (Examine the 0-successors of CEFG)
Partition #3.2
(Examine the 0-successors of CEFG) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

174. (Examine the 1-successors of CEFG)
Partition #3.2
(Examine the 1-successors of CEFG) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

175. (Examine the 1-successors of CEFG)
Partition #3.2
(Examine the 1-successors of CEFG) B C E
z=1
z=0
z=0 A
z=1 G
This needs to be
in a new block D
z=0
z=1 F
z=0

176. Partition #3
(ABD)(CEG)(F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

177. Partition #3
(ABD)(CEG)(F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

178. (Examine the 0-successors of ABD)
Partition #4.1
(Examine the 0-successors of ABD) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

179. (Examine the 1-successors of ABD)
Partition #4.1
(Examine the 1-successors of ABD) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

180. (Examine the 1-successors of ABD)
Partition #4.1
(Examine the 1-successors of ABD)
This needs to be
in a new block B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

181. Partition #4
(AD)(B)(CEG)(F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

182. Partition #4
(AD)(B)(CEG)(F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

183. (Examine the 0-successors of AD)
Partition #5.1
(Examine the 0-successors of AD) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

184. (Examine the 1-successors of AD)
Partition #5.1
(Examine the 1-successors of AD) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

185. (Examine the 0-successors of B)
Partition #5.2
(Examine the 0-successors of B) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

186. (Examine the 1-successors of B)
Partition #5.2
(Examine the 1-successors of B) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

187. (Examine the 0-successors of CEG)
Partition #5.3
(Examine the 0-successors of CEG) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

188. (Examine the 1-successors of CEG)
Partition #5.3
(Examine the 1-successors of CEG) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

189. (Examine the 0-successors of F)
Partition #5.4
(Examine the 0-successors of F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

190. (Examine the 1-successors of F)
Partition #5.4
(Examine the 1-successors of F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

191. Partition #5
(AD)(B)(CEG)(F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

192. Partition #4
(AD)(B)(CEG)(F) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

193. (This is the same as #4 so we can stop here)
Partition #5
(This is the same as #4 so we can stop here) B C E
z=1
z=0
z=0 A
z=1 G D
z=0
z=1 F
z=0

194. Minimized state table Nextstate Present Output state z w = w = 1 A B Cw = 1 A B C 1 B A F 1 C F C F C A
[ Figure 6.52 from the textbook ]

195. Multiplexers

196. 4-1 Multiplexer (Definition)
Has four inputs: w0 , w1, w2, w3
Also has two select lines: s1 and s0
If s1=0 and s0=0, then the output f is equal to w0
If s1=0 and s0=1, then the output f is equal to w1
If s1=1 and s0=0, then the output f is equal to w2
If s1=1 and s0=1, then the output f is equal to w3

197. Graphical Symbol and Truth Table
[ Figure 4.2a-b from the textbook ]

198. Using three 2-to-1 multiplexers to build one 4-to-1 multiplexerw w 1 1 f 1 w 2 w 3 1
[ Figure 4.3 from the textbook ]

199. Implementation of a logic functionw w w f 1 2 3 w w f 1 2 1 w 1 3 1 w 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(a) Modified truth table w 2 w 1 w 3 f 1
(b) Circuit
[ Figure 4.7 from the textbook ]

200. Implementation of 3-input XOR with a 4-to-1 Multiplexer2 3 w 3 1 1 1 1 w 3 1 1 1 1 w 3 1 1 1 1 w 3 1 1 1 1
[ Figure 4.9a from the textbook ]

201. Implementation of 3-input XOR with a 4-to-1 Multiplexer2 3 w 3 w 1 1 2 w 1 1 1 w 3 w 1 1 3 1 1 f w 3 1 1 1 1 w 3 1 1 1 1
(a) Truth table
(b) Circuit
[ Figure 4.9 from the textbook ]

202. Gated D Latch

203. Circuit Diagram for the Gated D Latch
[ Figure 5.7a from the textbook ]

204. Edge-Triggered D Flip-Flops

205. Master-Slave D Flip-FlopQ
Master
Slave
Clock m s
Clk
(a) Circuit
[ Figure 5.9a from the textbook ]

206. Negative-Edge-Triggered Master-Slave D Flip-FlopQ
Master
Slave
Clock m s
Clk
Positive-Edge-Triggered Master-Slave D Flip-Flop D Q
Master
Slave
Clock m s
Clk

207. Circuit Diagram for the Gated D Latch
[ Figure 5.7a from the textbook ]

208. Constructing a D Flip-Flop

209. Constructing a D Flip-Flop

210. Constructing a D Flip-Flop (with one less NOT gate)

211. Constructing a D Flip-Flop (with one less NOT gate)

212. T Flip-Flop

213. T Flip-Flop
[ Figure 5.15a from the textbook ]

214. Positive-edge-triggered
T Flip-Flop
Positive-edge-triggered
D Flip-Flop
[ Figure 5.15a from the textbook ]

215. T Flip-Flop
What is this?
[ Figure 5.15a from the textbook ]

216. What is this? Q T D

217. What is this? Q T D +
= ?

218. T Flip-Flop T D Q 1
Clock

219. What is this? +
= ?

220. T Flip-Flop T D Q
Clock

221. JK Flip-Flop

222. JK Flip-Flop
D = JQ + KQ
[ Figure 5.16a from the textbook ]

223. JK Flip-Flop ( ) (b) Truth table (c) Graphical symbol (a) Circuit J Q1 t + ( )
(b) Truth table
(c) Graphical symbol D
Clock
(a) Circuit
[ Figure 5.16 from the textbook ]

224. JK Flip-Flop (How it Works)
A versatile circuit that can be used both as a SR flip-flop and as a T flip flop
If J=0 and S =0 it stays in the same state
Just like SR It can be set and reset
J=S and K=R
If J=K=1 then it behaves as a T flip-flop

225. Registers

226. Register (Definition)
An n-bit structure consisting of flip-flops

227. A simple shift registerD Q
Clock In
Out t 1 2 3 4 5 6 7 =
(b) A sample sequence
(a) Circuit
[ Figure 5.17 from the textbook ]

228. Parallel-access shift register
[ Figure 5.18 from the textbook ]

229. Counters

230. A three-bit up-counter
[ Figure 5.19 from the textbook ]

231. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

232. A three-bit down-counter
[ Figure 5.20 from the textbook ]

233. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
[ Figure 5.20 from the textbook ]

234. Synchronous Counters

235. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

236. Synchronous Counter with D Flip-Flops

237. A four-bit counter with D flip-flops
[ Figure 5.23 from the textbook ]

238. Counters with Parallel Load

239. A counter with parallel-load capability
[ Figure 5.24 from the textbook ]

240. A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]

241. What does this circuit do?
[ Figure 5.25a from the textbook ]

242. Questions?

243. THE END