1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Mealy State Model CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff
Homework 9 is due today

4. Administrative Stuff Homework 10 is out
It is due on Monday Dec 2, 2013

5. Administrative Stuff Homework 10 is out
It is due on Monday Dec 2, 2013

6. Administrative Stuff Extra Credit Homework #2 is out
Posted on the class web page
There are 4 problems
Due no later than the last lab for this semester
Submit your design on paper and demonstrate your circuit to the lab TAs using the boards in the lab.

7. Administrative Stuff Final Project
Posted on the class web page (Labs section)
Pick one of the 4 problems and solve it.
Your grade will not depend on which project you pick
By this Friday you need to select your project number and that number to your lab TAs

8. Sample E-mail Hello TAs,
I decided to pick problem number x for my final project in CprE 281.
Thanks,
[your name]

10. The general form of a synchronous sequential circuitW
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock
[ Figure 6.1 from the textbook ]

11. Moore Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

12. Mealy Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

13. Sample Problem
Implement a 11 detector. In other words, the output should be equal to 1 if two consecutive 1’s have been detected on the input line. The output should become 1 as soon as the second 1 is detected in the input.

14. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
[ Figure 6.22 from the textbook ]

15. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

16. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

17. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

18. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

19. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

20. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

21. Sequences of input and output signals
Clock cycle: t 1 2 3 4 5 6 7 8 9 10 w : z
input
output
[ Figure 6.22 from the textbook ]

22. State diagram of an FSM that realizes the taskw = z 1 B
Reset
[ Figure 6.23 from the textbook ]

23. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
Reset

24. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
Reset

25. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset

26. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset

27. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset

28. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset

29. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

30. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

31. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

32. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

33. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

34. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

35. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

36. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

37. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

38. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

39. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

40. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

41. Let’s Do a Simulation input output Clock cycle: t w : z ¤ A w = z 1 B1 2 3 4 5 6 7 8 9 10 w : z
input
output A w = z 1 B
w = 0
z = 0
Reset
w = 1

42. Now Let’s Do the State Table for this FSM= z 1 B
Reset
Present
Next state
Output z
state w = 1 A B

43. Now Let’s Do the State Table for this FSM= z 1 B
Reset
Present
Next state
Output z
state w = 1 A B

44. The State Table for this FSM
Present
Next state
Output z
state w = 1 A B
[ Figure 6.24 from the textbook ]

45. Let’s Do the State-assigned Table
Present
Next state
Output z
state w = 1 A B
Next state
Output
Present
state w = w = 1 w = w = 1 y Y Y z z A B 1

46. Let’s Do the State-assigned Table
Present
Next state
Output z
state w = 1 A B
Next state
Output
Present
state w = w = 1 w = w = 1 y Y Y z z A 1 B 1 1 1

47. The State-assigned Table
Present
Next state
Output
state w = 1 y Y z A B
[ Figure 6.25 from the textbook ]

48. The State-assigned Table
Present
Next state
Output
state w = 1 y Y z A B
Y = D = w
z = wy
[ Figure 6.25 from the textbook ]

49. The State-assigned Table
Present
Next state
Output
state w = 1 y Y z A B
Y = D = w
z = wy
This assumes D flip-flop
[ Figure 6.25 from the textbook ]

50. Circuit Implementation of the FSM
Clock
Resetn D Q w z y
Y = D = w
z = wy
[ Figure 6.26 from the textbook ]

51. Circuit & Timing Diagramz w D Q y
Clock Q
Resetn
(a) Circuit t t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 1
Clock 1 w 1 y 1 z
[ Figure 6.26 from the textbook ]
(b) Timing diagram

52. What if we wanted the output signal to be delayed by 1 clock cycle?

53. Circuit Implementation of the Modified FSM
[ Figure 6.27a from the textbook ]

54. Circuit Implementation of the Modified FSM
This flip-flop delays the
output signal by one clock cycle
[ Figure 6.27a from the textbook ]

55. Circuit & Timing Diagram
[ Figure 6.27 from the textbook ]

56. The general form of a synchronous sequential circuitW
Combinational
Combinational
Flip-flops Z
circuit
circuit Q
Clock
[ Figure 6.1 from the textbook ]

57. Moore Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

58. Mealy Type W Combinational Combinational Flip-flops Z circuit circuitQ
Clock

59. Moore Mealy

60. Moore Mealy

61. Mealy
Moore

62. Questions?

63. THE END