FLIP FLOPS Binary unit capable of storing one bit – 0 or 1 Flip Flop has two stable states and a transition between these two states . Transition is depended on input. HIGH LOW HIGH / 1 / SET LOW / 0 / RESET Transition between states 0 / 1 Input

Types of FLIP FLOPS FLIP FLOP RS Flip Flop JK Flip Flop T Flip Flop D Flip Flop

RS - FLIP FLOP Block Diagram RS Flip Flop R S Q

RS - FLIP FLOP RS Latch using NOR Gate R S A B Q

RS - FLIP FLOP R Q S TRUTH TABLE A B R S Q NC 1 SET RESET * Case 1 NC 1 SET RESET * Case 1 Case 2 Case 3 Case 4 NO CHANGE R S A B Q 1 1 1 1

RS - FLIP FLOP R Q S TRUTH TABLE A B R S Q NC 1 SET RESET * Case 1 NC 1 SET RESET * Case 1 Case 2 Case 3 Case 4 SET R S A B Q 1 1 1

RS - FLIP FLOP R Q S TRUTH TABLE A B R S Q NC 1 SET RESET * Case 1 NC 1 SET RESET * Case 1 Case 2 Case 3 Case 4 RESET 1 R S A B Q 1 1

RS - FLIP FLOP R Q S TRUTH TABLE A B R S Q NC 1 SET RESET * Case 1 NC 1 SET RESET * Case 1 Case 2 Case 3 Case 4 RACE CONDITION 1 R S A B Q 1

RS - FLIP FLOP R Q S RS Latch using NAND Gate (RS Flip Flop) A B R S Q * 1 SET RESET NC

RS - FLIP FLOP R Q S RS Latch using NAND Gate A B 1 Race Condition 1 1 1 Race Condition R S A B Q 1 1 1 R S Q * 1 SET RESET NC

RS - FLIP FLOP R Q S RS Latch using NAND Gate (RS Flip Flop) A B 1 1 1 R S A B Q 1 1 1 1 1 R S Q * 1 SET RESET NC

RS - FLIP FLOP R Q S RS Latch using NAND Gate A B 1 1 1 1 1 R S Q * 1 1 1 1 R S Q * 1 SET RESET NC

RS - FLIP FLOP R Q S RS Latch using NAND Gate A B 1 1 1 1 1 1 R S Q * 1 1 1 1 R S Q * 1 SET RESET NC

Clocked RS Flip Flop A Clock signal is added to the input What is the Difference ???? A Clock signal is added to the input What Clock Signal will do ???? Clock Signal controls the instant at which flip flop changes the state How to Design ??? Basic NOR- Flip Flop + Two AND Gates + A Clock Signal nnn R S CLK Q

Clocked RS Flip Flop Rule of RS Flip Flop : Block Diagram of Clocked RS Flip Flop R S CLK Q Rule of RS Flip Flop : Q is always complement of Q

TRUTH TABLE R S CLK Qn Qn+1 ACTION Case NC 1 2 3 4 5 6 SET 7 8 9 10 NC 1 2 3 4 5 6 SET 7 8 9 10 RESET 11 12 13 14 ? ERROR 15 16

Case 1 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION NC nnn R S CLK Q 1 NC nnn R S CLK Q 1 1 1 1

Case 2 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q 1 NC nnn R S CLK Q 1 1

Case 3 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q 1 NC nnn R S CLK Q 1 1 1 1 1

Case 4 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q 1 NC nnn R S CLK Q 1 1 1

Case 5 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q 1 NC nnn R S CLK Q 1 1 1 1 1

Case 6 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q 1 NC nnn R S CLK Q 1

Clocked RS Flip Flop Case 7 R S CLK Qn Qn+1 ACTION 1 SET nnn R S CLK Q

Clocked RS Flip Flop Case 8 R S CLK Qn Qn+1 ACTION 1 SET nnn R S CLK Q

Clocked RS Flip Flop Case 9 R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q

Clocked RS Flip Flop Case 10 R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q

Case 11 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 RESET nnn R S RESET nnn R S CLK Q

Case 12 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 RESET nnn R S RESET nnn R S CLK Q

Clocked RS Flip Flop Case 13 R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q

Clocked RS Flip Flop Case 14 R S CLK Qn Qn+1 ACTION 1 NC nnn R S CLK Q

Case 15 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 ? ERROR nnn R S ? ERROR nnn R S CLK Q

Case 16 Clocked RS Flip Flop R S CLK Qn Qn+1 ACTION 1 ? ERROR nnn R S

D – Flip Flop (Delay Flip Flop) (Clocked) Stores digital info Has Single input It does not have Race Condition D Flip Flop = One RS Latch + One Inverter Single Input D Flip Flop D Clk Q

D – Flip Flop (Delay Flip Flop) (Clocked) D Flip Flop using NAND Gate When Clock is LOW : AND gates of Flip Flop are ENABLE When Clock is HIGH : AND gates of Flip Flop are DISABLE D CLK Q Single Input

D – Flip Flop (Delay Flip Flop) (Clocked) Truth Table Clock Input ( D) Output (Q) 1 x No Change bb D CLK Q 1 1 1 1 1 1 1

D – Flip Flop (Delay Flip Flop) (Clocked) Truth Table Clock Input ( D) Output (Q) 1 x No Change fff D CLK Q 1 1 1 1 1 1 1

D – Flip Flop (Delay Flip Flop) (Clocked) Truth Table Clock Input ( D) Output (Q) 1 x No Change D CLK Q 1 1 1 1 1 1 1

D – Flip Flop (Delay Flip Flop) (Clocked) Truth Table Clock Input ( D) Output (Q) 1 x No Change D CLK Q 1 1 1 1 1 1 1

D – Flip Flop (Delay Flip Flop) (Clocked) State Transition Diagram Q (t) D Q (t+1) 1 1 D

JK Flip Flop Similar to SR Flip Flop Input J and K behaves like SET and RESET When J = K = 1, the Flip Flop Output Toggles If Q = 0, it switches to 1 if Q = 1, it switches to 0

JK Flip Flop using SR Flip Flop CLK Q J K S = J . Q R =K. Q J K CLK Q

X JK Flip Flop X X X S = J . Q J K R =K. Q S R Q Clock Inputs Output CLK Q J K S = J . Q R =K. Q X X Clock Inputs Output Qn+1 Action J K X Qn NC 1 RESET SET TOGGLE

JK Flip Flop S = J . Q J K R =K. Q S R Q 1 1 Clock Inputs Output Qn+1 CLK Q J K S = J . Q R =K. Q 1 1 Clock Inputs Output Qn+1 Action J K X Qn NC 1 RESET SET TOGGLE

JK Flip Flop S = J . Q J K R = K. Q S R Q 1 1 1 Clock Inputs Output CLK Q J K S = J . Q R = K. Q 1 1 1 Clock Inputs Output Qn+1 Action J K X Qn NC 1 RESET SET TOGGLE

JK Flip Flop S = J . Q J K R =K. Q S R Q Clock Inputs Output Qn+1 CLK Q J K S = J . Q R =K. Q Clock Inputs Output Qn+1 Action J K X Qn NC 1 RESET SET TOGGLE

Ripple Counter

Basic Concepts 1. A ripple counter consists of two or more T flip=flops inter connected so that the output of each flip-flop is connected to the T input of the following flip-flop. 2. The ripple counter is also called an asynchronous counter since the output states do not change simultaneously with a common clock. 3. Ripple counters can be made to count up or down.

Basic Concepts 4. The direction of count can be reversed by complementing the output of each flip- flop. 5. The direction of count can also be reversed by complementing the input of each flip- flop.

Introductory Information Counters fall into two basic groups: serial and parallel. The serial counter (or asynchronous counter) is referred to as a ripple counter since each flip-flop is triggered one at a time, with the output of one flip-flop to triggered the next flip-flop. In a parallel counter (synchronous counter), all the flip-flops are triggered at the same time. The parallel counter will be discussed in a later lesson.

Introductory Information Counters may count each operation in one area and, after a predetermined number of operations have been performed (counted), it could initiate another set of operations in a different area. Another use of counters is to control the timing of operation sequences. In this application, it provides control signals (commands) to different areas of operations at predetermined intervals (a set numbers of counts for each operation).

Objective A. Identify the basic digital ripple counter and it's logic function as an up-counter. Preparatory Information . A basic 4-bit ripple counter is shown in Fig. 11-1 (a). Each flip-flop is connected to operate as a T flip-flop (all the J and K inputs must connect to a HI ) . Notice that the Q output of each flip-flop is connected to the clock input of the following flip-flop. In this way, each flip-flop will triggered by the preceding flip-flop.

Fig.11.1 (b) is a timing diagram showing the Q output of each flip-flop relative to the input clock. The flip-flops trigger on the negative edge of their clock pulse in our example . Hence, flip-flop A does not change logic states (toggle) until the input clock goes from HI to LO (negative edge). Likewise, flip=flop B, C, and D do not toggle until the negative edge from the preceding flip-flop occurs.

Objective B. Demonstrate how the basic ripple counter can be made to function as a down counter. Preparatory Information. The binary up-counter of Fig. 11-2 may be change to a binary down-counter in either of two ways: (1) by triggering each flip-flop with the Q output but using the Q outputs to indicate the binary count (complementing the Q output of each flip-flop), Fig. 11.3 (a); or (2) by using the Q outputs to indicate the binary count but triggering each flip-flop with the Q output (complementing the input of each flip-flop), Fig. 11.3 (b).

When changing from up-counter to a down-counter by a method (2), we can leave the Q outputs connected to the indicators, as in the up-counter, but connect the Q outputs to the clock inputs of each flip-flop. This method can be analyzed in the same manner as the up counter. Fig 11.4 is a partial timing diagram of the four flip-flop Q and Q outputs.

Objective C. Demonstrate how a ripple counter may be made to count up or down on command by using control logic gates. Preparatory Information. With the addition of control logic gates we can have one counter circuit that will count up or down upon command. A 4-bit up-down binary counter is shown in Fig.11.5 Gates A through J control the up and down count functions. Remember that the AND gates any LO output and only when both inputs are LO will the output be HI.

Also remember that for NOR gates any HI produces a LO output and only when both inputs are LO will the output be HI. The NOR output will complement the count sequences described in objective A or B. In other words, when gates A, D and G are enable by LO at the up/down input, the Q outputs are inverted by the NOR gate. Therefore the Q outputs are effectively connected to the clock inputs causing the counter to count down. A HI at the up/down input enables gate B, E, and H and the Q outputs are also inverted by the NOR gates. Hence, the Q outputs are effectively connected to the clock inputs causing the counter to count up.

Post-test 1. The counter discussed in this Laboratory Exercise : a. A binary counter b. A ripple counter c. An asynchronous counter d. All of the above 2. A ripple counter can be made to count: a. Up b. Down c Up and Down

3. A five-stage ripple counter provides a frequency division of: a. 16 b. 24 c. 32 d. 36 4. If a binary counter consisted of five flip-flops, what be the maximum decimal count? a. 15 b. 16 c. 31 d. 32 5. If it is desired to have a binary counter capable of attaining a maximum count of 63, how many flip-flops would be required? a. 4 b. 5 c. 6 d. 7