LAB #6 Sequential Logic Design (Flip Flops, Shift Registers) ENG2410 Digital Design LAB #6 Sequential Logic Design (Flip Flops, Shift Registers)

Lab Objectives Understand the concept of sequential circuit. Understand sequential circuit design flow. Design a simple D Flip Flop using behavioural VHDL Design a Shift Register using structural VHDL. ENG241/Lab #6

Part 1 D Flip Flop Design D-FF with asynchronous reset logic using VHDL. Use an LED to display the output of the FF. ENG241/Lab #6

Sample Sequential Circuit Positive Edge-Triggered D Flip-Flop Note that this FF does not have a “reset” input library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dff is port ( d , clk : in std_logic; q , qbar : out std_logic); end dff; architecture behaviour of dff is begin Up : process (clk,d) if clk’event and clk = ‘1’ then q <= d; qbar <= not d; end if; end process; end behaviour; ENG241/Lab #6

Positive Edge Triggered D-FF with Reset -- positive Edge-Triggered D flip-flop with reset -- VHDL Process Description library ieee; use ieee.std_logic_1164.all; entity dff is port (CLK, RESET, D : in std_logic; Q : out std_logic); end dff; architecture pet_pr of dff is begin process (CLK, RESET) if (RESET = `1’) then Q <= `0’; elsif (CLK’event and CLK = `1’) then - - you can use rising_edge(CLK) instead! Q <= D; end if; end process; end;

Part 2 4 Bit Shift Register Design D-FF with asynchronous reset logic. Build 4-bits shift register using the modified D-FF. Use LEDs to display the output of each FF. ENG241/Lab #6

Academic Misconduct Reports and demos are submitted as a group, but it is a SINGLE group effort You may talk with other groups but sharing codes or reports is NOT ALLOWED Copying reports from previous years is also NOT ALLOWED If we find copying we are REQUIRED to report it