Input / Output Chapter 9

Introduction I/O – predominant factor in computers LMC I/O baskets correspond to a set of busses and registers in a hardware I/O module Programmed I/O (data is transferred one word at a time) Complicating factors: Programmed I/O needs to be complemented by block data transfer Many I/O devices. Need: Device identification Synchronization of operations I/O operations take a lot of computer time. Need to run them in parallel with CPU activity

Background There is the Operating System: Manage I/O devices and data transfer operations Manage multiple programs Provides and manage GUI

Characteristics of typical I/O devices Characteristics of I/O devices affect computer performance Ex1: Keyboard Slow; data is transferred one word at a time Two types of input: expected and unexpected (unpredicted) <Ctrl-C>, <Ctrl-Alt-Del> Possibly many keyboards Ex2: disks Data can be transferred in blocks; fast Possible many disks Ex3: network interfaces

Characteristics of typical I/O devices I/O operations are typically initiated by programs, but sometimes I/O devices need to initiate them too Devices are connected to the CPU via hardware I/O modules (device controllers) Requirements for efficient I/O. Must have: Individual addressing of I/O devices Method for devices to initiate communication with the CPU Programmed I/O for slow devices; non-programmed I/O for fast devices Means to handle uniformly very different devices

Differences in I/O devices Data format: One piece of data to blocks of data Parallel and sequential transmission Speed and synchronization Data flow Electromechanical requirements must be met

Examples of I/O Devices Device Input/Output Date Rate (Kbytes/s) Keyboard Input 0.01 Mouse Input 0.02 Voice input (microphone) Input 0.02 Scanner Input 200 Voice output (speaker) Output 0.5 Dot-matrix printer Output 1 Laser printer Output 100 Graphics display Output 30,000 Local area network Input/output 200 – 20,000 Optical disk Storage (I/O) 500 Magnetic tape Storage (I/O) 2,000 Magnetic disk Storage (I/O) 2,000

Programmed I/O I/O operations are under direct control of software (program) Software initiates the I/O operation Disadvantage: Slow (data is transferred one word at a time) Uses a lot of CPU resources Advantage: Simple

Simple I/O configuration

More complex I/O module arrangement Multiple devices

I/O Configurations (1 of 2) CPU Keyboard Mouse Voice input (microphone) Scanner Voice output (speaker) Dot-matrix printer Laser printer Graphics display Local area network Optical disk Magnetic tape Magnetic disk Can take many forms, e.g., Sound card controller Disk controller I/O module I/O device

I/O Configurations (2 of 2) CPU Data bus Address bus Control bus I/O data I/O address I/O control I/O module I/O module I/O device I/O device I/O device

Types of I/O Programmed I/O Direct memory access (DMA) Interrupts are used for both types

Programmed I/O (1/2)

Programmed I/O (2/2)

Interrupts Used to: I/O operations are initiated by the device Stop the normal execution of the current program and do other processing Implement system events I/O operations are initiated by the device The device, or its I/O module, includes a signal to interrupt the CPU These signals are called interrupt lines A typical CPU supports 8 to 16 interrupt inputs Typical names: IRQ1, IRQ2, IRQ3, etc.

Basic CPU-memory-I/O pathway

Interrupts Interrupt lines (hardware) Interrupt request One or more special control lines to the CPU Interrupt request Interrupt handlers Program that services the interrupt Also known as an interrupt routine or device driver Context Saved registers of a program before control is transferred to the interrupt handler Allows program to resume exactly where it left off when control returns to interrupted program

Use of Interrupts Notify that an external event has occurred Real-time or time-sensitive Signal completion Printer ready or buffer full Allocate CPU time Time sharing Indicate abnormal event (CPU originates for notification and recovery) Illegal operation, hardware error Software interrupts

Example Many keyboards – input is coming from each of them Processing input can be done Theoretically: by using polling (wastes computer time) Practically: by using interrupts (keyboard key  interrupt line  CPU)

Servicing an Interrupt When an interrupt occurs (and is accepted), the execution of the current program is suspended Must save PC, Registers in Program Control Block (PCB) A special routine executes to service the interrupt In most cases the interrupted program resumes The service routine is called an interrupt handler or interrupt service routine (ISR)

Servicing an interrupt

Saving Registers For the interrupted program to resume, the CPU status and data registers must be saved (because they will change during the ISR) They are saved before the ISR executes They are restored after the ISR executes They are saved either On the stack (a special area of memory to temporarily hold information), or In a process control block (PCB)

Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator As software generated interrupts

Interrupts for External Events An interrupt signal occurs when an “event” occurs in a device – an event that requires the CPU’s attention E.g., Keyboard: a key has been hit (the ISR reads the code for the key) Notebook computer cover: the cover is closed (the ISR puts the computer in standby mode)

Using a keyboard handler interrupt

Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator As software generated interrupts

Using a print handler interrupt

Interrupts for Completion Signals An interrupt signal occurs when a device has completed an operation – and the CPU should know about it E.g., Printer: the output buffer is empty (the CPU can send more data) Scanner: a data transfer is complete (the CPU/application can proceed to process the image data)

Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator As software generated interrupts

Interrupts for Allocating CPU Time Useful on multi-tasking systems – systems that can execute more than one program at a time E.g., A timer is programmed to interrupt the CPU every 100 µs (for example) The ISR is a “dispatcher program” Execution switches to another program (for 100 µs), etc.

Using an interrupt for time sharing

Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator As software generated interrupts

Interrupts for Abnormal Events An interrupt signal occurs when an abnormal event occurs that needs immediate system attention E.g., A heat sensor near the CPU chip – if the temperature is too high, an interrupt is generated, the ISR activates the fan near the CPU chip

Use of Interrupts As an external event notifier As a completion signal As a means of allocating CPU time As an abnormal event indicator As software generated interrupts

Software interrupts Example: IBM SuperVisor Call Used to force a jump/branch to a certain location Application: centralize I/O

Multiple interrupts and prioritization Processing an interrupt requires: Interrupt source? Are there other interrupts to be serviced? Interrupt source (see next slides) Interrupt vector Polling

Vectored interrupt processing

Polled interrupt processing

Multiple interrupts Are handled by: See next slide Assigning priorities Disabling other interrupts for a period of time See next slide Interrupts are checked at the end of each instruction

Multiple interrupts

Direct Memory Access Used for high-speed block transfers between a device and memory During the transfer, the CPU is not involved Typical DMA devices: Disk drives, tape drives Remember (1st slide) Keyboard data rate  0.01 KB/s (1 byte every 100 ms) Disk drive data rate  2,000 KB/s (1 byte every 0.5 µs) Transfer rate is too high to be controlled by software executing on the CPU

Program-Controlled I/O (in DMA) CPU Data bus Address bus Control bus The CPU “prepares” the DMAC Memory DMAC Disk

DMA Data bus Address bus Control bus CPU The transfer takes place DMAC Memory DMAC Disk

I/O Interrupt (in DMA) Data bus Address bus Control bus CPU The DMAC interrupts the CPU when the transfer is complete IRQ Memory DMAC Disk

How The CPU “prepares” the DMA operation by transferring information to a DMA controller (DMAC): Location of the data on the device Location of the data in memory Size of the block to transfer Direction of the transfer Mode of transfer (burst, cycle steal) When the device is ready to transfer data, the DMAC takes control of the system buses (next few slides)

“Taking Control” (1 of 2) CPU DMAC Control Bus signals BR BG BGACK BR BR = Bus request (DMAC: May I take control of the system buses?) BG = Bus grant (CPU: Yes, here you go.) BGACK = BG acknowledge (DMAC: Thanks, I’ve got control.)

“Taking Control” (2 of 2) DMAC issues a BG (“bus request”) signal CPU halts and issues a BG (“bus grant”) signal DMAC issues BGACK (“bus grant acknowledge”) and releases BR DMAC has control of the system buses DMAC “acts like the CPU” and generates the bus signals (e.g., address, control) for one transfer to take place Then…

DMA Transfers (2 of 2) Burst mode Cycle steal mode This transfer is repeated until complete DMAC relinquishes control of the system buses by releasing BGACK Cycle steal mode A BR-BG-BGACK sequence occurs for every transfer, until the block is completely transferred DMAC interrupts the CPU when the transfer is complete This is an example of a “completion signal” interrupt