Status of hardware activity in CNS Taku Gunji Center for Nuclear Study University of Tokyo 1

Detector Design W+Si calorimeter W thickness: 3.5 mm Si pad size: 1.1x1.1cm 2 (64 ch/pad) wafer size: 9cmx9cmx0.525mm W+Si pad : 21 layers 3 longitudinal segments Summing up raw signals in segments longitudinally (64ch/segment) Similar to PHENIX design Strip readout: 0.7mm(128ch/wafer) Option: Use MIMOSA type pixel layers instead of strip layers Size: 9x9 cm 2 Thickness: 535  m Pad size: 1.1x1.1 cm 2 Number of pads : 64 2

Readout Flow Composition – Summing board : sum up signals in segments longitudinally (64*3 + X lines) – ASIC cards Preamplifer + shaper (analog out) or preamplifer with QTC (digital out) – ADC(12-14bit)/TDC(TMC)+FPGA board Digitizer, ZS, feature extraction, formatting, trigger handling, buffering – SRU (scalable readout unit) Developed by RD51. Will be used for EMCAL/DCAL Scalable Readout Unit (HDMI/Flat?) Fast analog/digital out for trigger? ASIC Summing board ADC/TDC/FPGA 3

Jig for assembling First prototype jug for assembling the pad layers – Dummy material + summing board + HIROSE FPC/FFC connector – Will be developed with iterations. Summing board Dummy material (3.5mm thickness plate + flexible cables) HIROSE FPC/FFC connector 4

ASIC development Pi0 gamma from pi0 prompt photon 10 4 Requirements : – Annual pi0 yield estimated using PYTHIA(p+p)/HIJING(p+Pb) More careful study (higher pT and NLO inclusion) will be done. Preliminary pT reach < GeV/c in annual p+p running under L=10 30 cm -2 s -1. – Dynamic range : Input energy: MIP – 500 GeV Deposit energy in 2 nd segment: 1.2 MeV – 5 GeV Charge : 50 fC – 200pC Dual preamplifer with capacitive division – Works if open loop gain is high. – Need to protect saturation in high gain side. C low C high SA(high gain) SA(low gain) C low = 0.1*C high 5

ASIC development (contd.) First prototype by RIKEN: – Good linearity up to 1.5 GeV – S/N = 10 (for 1.2MeV) Development by CNS : – Optimize preamplifier – Two types of readout : Add PZ/dual integrator (t peak =2usec) Add PZ/dual integrator + QTC Linearity : MeV – 1.5GeV 200pC 100pC These ASIC will be available by Feb Another type of QCT is under design. 6 highlow high low

Backup slides

Another type of readout Charge to time converter (QTC) – Pros: No digitizer. Just use FPGA (<1GHz) as TDC/TMC Not limited by the input range of ADC Reduce power consumption for signal driving Flexible for the range and adjustable according to rate – Cons: Noise – Primitive version to be made to see how feasible it is. Sample/hold + current source + CMOS switches Alternative QTC design is on going (integrator + current source without switches). 8

Block diagram and linearity From shaper To Comparator, LVDS driver high low Block diagram for prototype – Two lines after the shaper : comparator + LVDS driver (for self trigger/start generation) QTC + comparator + LVDS driver – 5pF as sampler, 2.5uA as current  range <2.5V/(2.5uA/5pF) = 5usec – The current is adjustable to enlarge the range and resolution per bit 9

ADC/TDC & FPGA board At least, 10 bit is not enough. More than 12 bit. – Commercial FADC (TI, AD,,,) with multi-channel/chip, 10-50MSPS, low power consumption – Roughly speaking, data size in p+A could be: 0.3(occupancy) x 256 (tower) x 64 x 3 (ch/tower ) x 2 (H/L) x 12 (bit) x 20 (# of samples) = 0.9MB/event – Reference: dN/dy=700, 15MB/evt (TPC), 1.1MB/evt (TRD) Need to extrapolate to A+A – FPGA (Xilinx Virtex series) for zero suppression, feature extraction (online pulse shape analysis, summation), event building, formatting, trigger input handing, output buffering (and send to SUR) – Similar to TRU in PHOS/EMCAL. 10

FEE & SRU Use SRU as EMCAL/DCAL/(TPC) will do. – developed by RD51+ALICE project TTCrx interface for trigger handling 10 GBE, SPF, optical fiber Master for the slow control of FEEcards 11

Scheme: FEE and SRU 12