1. PRAD DAQ System Overview
PRad DAQ computer
Linear Sum
Gate for Fastbus ADCs
Trigger to TI master
Trigger to TI slaves
JLab network
Data/Control
Timing information to JLab discriminators
GEM
SRS
Crate
Trigger to SRS
Logic and Translation
TI Slave
CPU
TI Slave
CPU
TI Slave
CPU
TI Master
CPU
This is essentially a copied slide
(Fig. courtesy of Chao Peng)

2. A typical CODA event with SRS Data
SRS Data Frame header.
A typical CODA (2.6.2) event viewed with “xcefdmp” utility showing SRS data bank and various other information.

3. Raw SRS Output With GEM/APV signals
GEM hits
ADC
Time
Sync pulses

4. Conclusion Successful integration of SRS with CODA
Event rate studies going on.

5. Backup Slides

6. Scalable Readout System (SRS)
Developed by RD51 collaboration at CERN
Flexibility in choosing the chip frontend (ASIC, hybrid) for a detector readout
Possibility of a common readout backend with standard DAQ Software
Uses links instead of buses: more reliable, longer distance and more bandwidth
Scalibility - start from minimal systems (few links, 1 SRU) -> if needed scale to large systems (more links and SRUs)
Combines 3 streams: single DTC (Data, Trigger, Control) link (copper or fiber)
Cheap & standard: frontend card chassis (Eurocard format), cables (CAT6 cable) , fibers (850 nm MM fiber), network (10 Gigabit Ethernet)
Robust, user-friendly and not-so-difficult to integrate with existing DAQ systems
Radiation protected on FEC and SRU FPGA chips
from:

7. SRS Minicrate - a portable solution for up to 4k channels
Cosmic Ray Test
Current tests done with a small (15×15) GEM and 6 APV25 hybrids connected to a single FEC-ADC pair.
Approximate rate of 0.8 Hz using coincidence signals from cosmic rays.
SRS Minicrate - a portable solution for up to 4k channels

8. Raw SRS Pedestal Output

9. Raw SRS Output With GEM/APV signals

10. Picture source: http://test-rd51-wg5-v2. web. cern

11. Scalable Readout System (SRS)
Developed by RD51 collaboration at CERN
A copied slide (not mine) – just for reference.
2 × 12-Bit Octal ADC
8 × HDMI input channels (16 APV hybrids)
Virtex LX50T FPGA
SFP/Gb Ethernet/DTC interface
NIM/LVDS GPIO (trigger, clock synch, etc.)
128 channel APV25 chip
192-deep analog sampling memory
Master/slave configuration
Diode protection against discharge
RD51 standard 130-pin Panasonic connector interfaces to detector
Mini HDMI (type C) connector
Data Acquisition using CODA (JLab)
Data transfer via UDP
Slow control via ethernet

12. Eurocrate a scalable solution for up 16 k channels/crate
HP version up 4 FECs, 1 ATX, incl. power for 64 hybrids
FP version up 8 FECs, 2 ATX, incl. power for 128 hybrids
ATX power adapter
A copied slide (not mine) – just for picture reference
CTF Trigger and Clock
Fanout in SRS slot 9
8 x ADC card
from backside
8 x FEC card
from frontside