THEMIS Instrument CDR 1 UCB, April 20, 2004 Actel Reliability Critical Design Review Robert Abiad University of California - Berkeley

THEMIS Instrument CDR 2 UCB, April 20, 2004 Actel Overview Overview of Actel SX-S Field Programmable Gate Array 2012 flip-flops 4024 combinatorial modules 5V I/O supply 2.5V internal supply >200 MHz performance Output ps rise time for commercial part Output 2 ns low-slew fall time for commercial part

THEMIS Instrument CDR 3 UCB, April 20, 2004 Actel Difficulties Metastability Violation of flip-flop setup time resulting in undefined output Solution - Add another synchronizing flip-flop

THEMIS Instrument CDR 4 UCB, April 20, 2004 Actel Difficulties Glitch Sensitivity Flip-flops respond to ns glitches Solution - Sample clock input where glitches will create failures

THEMIS Instrument CDR 5 UCB, April 20, 2004 Actel Difficulties Power On Reset Can cause timing violations if removed asynchronously to flip- flop inputs. Solution - Assert asynchronously, but de-assert synchronously

THEMIS Instrument CDR 6 UCB, April 20, 2004 Actel Difficulties Clocks Only HCLK is absolutely guaranteed Use as main clock CLKA/CLKB are susceptible to too much skew Use with caution QCLKA/B/C/D are guaranteed in their quadrants but not outside Use with caution Unused clocks must be grounded.

THEMIS Instrument CDR 7 UCB, April 20, 2004 Actel Difficulties Timing Analysis Must be done Easiest when design is synchronous Less repeatable when the part is closer to full.

THEMIS Instrument CDR 8 UCB, April 20, 2004 Actel Difficulties Ground Bounce The momentary difference between the ground inside an IC and on a PCB caused by the transition of I/Os on the IC to ground. The result of inductance between the IC ground and the PCB. Can cause receiving flip-flops to clock. Can temporarily increase the array voltage on Actels and destroy antifuses. Solutions Separate simultaneously switching I/Os Provide the shortest path to ground as possible for parts Use low slew outputs on Actel pins Install resistors in series with signals that may glitch

THEMIS Instrument CDR 9 UCB, April 20, 2004 Actel Difficulties Power Decoupling Best to have a mix of decoupling capacitor sizes (100nF, 10nF, 1nF) Use short, fat traces Utilize interplane capacitor

THEMIS Instrument CDR 10 UCB, April 20, 2004 Actel Difficulties Signal Integrity Fast signals on long traces ring - use termination Signals that travel near each other talk Separate sensitive signals Route traces in opposite directions on adjacent layers Slow signals down - low slew or series termination Keep a reference plane adjacent to signal layers Clock edges need to be just right Slow edges cause multiple transitions Fast edges create noise Stubs increase noise - don’t use on sensitive signals