EE412 Deep Trench Spray Coating Final Presentation Karthik Vijayraghavan Mentor : Jason Parker 12/08/2010 1.

Slides:



Advertisements
Similar presentations
VOC Emissions Reduction from Photolithographic Processes
Advertisements

Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.
Advanced Manufacturing Choices
COUNCIL FOR THE CENTRAL LABORATORY OF THE RESEARCH COUNCILS EAP dimple fabrication process. Process D EAP dimple using carbon powder electrodes and DRIE.
Photolithography PEOPLE Program July 8, Computer chips are made using photolithography Instead of drawing with a sharp tip, it uses light to transfer.
Lithography – Basic Concept
John D. Williams, Wanjun Wang Dept. of Mechanical Engineering Louisiana State University 2508 CEBA Baton Rouge, LA Producing Ultra High Aspect Ratio.
Effect of Resist Thickness
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
Optical Lithography Ghassan Malek Sr. Development Engineer October 6, 2010 Integrated Systems Nanofabrication Cleanroom.
Etching Film deposition Photoresist coating Lithography Development Film etching Together with calibration sample Optical inspection Measure photoresist.
Pattern transfer by etching or lift-off processes
SPRAY COATER REPORT Pierre Ponce 4/15/2010. Operation The AccuMist nozzle is NOT centered when the head is at the 0 angle position – Tested using Center.
Lampoly etch profiles Courtesy of Rishi Kant (Coral name: rik) Performed: 11/18/08 Wafer: Silicon substrate patterned with a thermal oxide hard mask (6000.
EE412: EVG Spraycoater Characterization Project Owner: Mahnaz Mansourpour Project Mentor: Jason Parker Student Investigator: Ehsan Sadeghipour 1/12/2011.
MEMS Cell Adhesion Device Andrea Ho Mark Locascio Owen Loh Lapo Mori December 1, 2006.
Zarelab Guide to Microfluidic Lithography Author: Eric Hall, 02/03/09.
Wafer processing - I Clean room environment Semiconductor clean room: - controlled temperature (20ºC), air pressure, humidity (30%) - controlled airbone.
1 Microfabrication Technologies Luiz Otávio Saraiva Ferreira LNLS
SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.
ECE/ChE 4752: Microelectronics Processing Laboratory
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
Top Down Method Etch Processes
Lecture 4 Photolithography.
5x mixed with 25x Reduction 1.Draw mask, keeping 25x features within a 3mm square, within the traditional 14-15mm 5x die 2.When printing masks scale 25x.
Lithographic Processes
Micro-fabrication.
Fabrication of Active Matrix (STEM) Detectors
CNT Based Solar Cells MAE C187L Joyce Chen Kari Harrison Kyle Martinez.
MOHD YASIR M.Tech. I Semester Electronics Engg. Deptt. ZHCET, AMU.
Contrast Properties of Electron Beam Resist Ahmed Al Balushi.
Nano/Micro Electro-Mechanical Systems (N/MEMS) Osama O. Awadelkarim Jefferson Science Fellow and Science Advisor U. S. Department of State & Professor.
II-Lithography Fall 2013 Prof. Marc Madou MSTB 120
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
Introduction to Prototyping Using PolyMUMPs
Top Down Manufacturing
Top Down Method Etch Processes
Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.
Center for Materials for Information Technology an NSF Materials Science and Engineering Center Optical Lithography Lecture 13 G.J. Mankey
1 Spray cooling on micro structured surfaces Paper review.
ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
LITHOGRAPHY IN THE TOP-DOWN PROCESS - BASICS
Bump Bonding Development
C Virginia Tech Effect of Resist Thickness Resists usually do not have uniform thickness on the wafer –Edge bead: The build-up of resist along the.
Fab - Step 1 Take SOI Wafer Top view Side view Si substrate SiO2 – 2 um Si confidential.
(Chapters 29 & 30; good to refresh 20 & 21, too)
Roughness and Electrical Resistivity of Thin Films Spencer Twining, Marion Titze, Ozgur Yavuzcetin University of Wisconsin – Whitewater, Department of.
Date of download: 11/12/2016 Copyright © 2016 SPIE. All rights reserved. A sketch of a micro four-point probe with integrated CNTs in situ grown from nickel.
Equipment and technological processes for manufacturing GaAs MMICs LITHOGRAPHY ONE TALK 3 1.
Wisconsin Center for Applied Microelectronics
EE 3311/7312 MOSFET Fabrication
Pt-Ox Test Results Wafer Processing and SEM by Kenneth Leedle
ALD Fiji for Conformality Test
Lithography.
Manufacturing Process I
Lecture 4 Fundamentals of Multiscale Fabrication
1) Wafer Cleaning Oxidizing – Field Oxide
High Aspect Ratio Si Etching in STS2
MEMS, Fabrication Cody Laudenbach.
Fab. Example: Piezoelectric Force Sensor (1)
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device State and explain the principles involved in attaining good mask.
Lithography Layout, Mask, photo.
Memscap - A publicly traded MEMS company
Manufacturing Process I
LITHOGRAPHY Lithography is the process of imprinting a geometric pattern from a mask onto a thin layer of material called a resist which is a radiation.
Manufacturing Process I
Photolithography.
1) Wafer Cleaning Oxidizing – Field Oxide (~130 nm)
Presentation transcript:

EE412 Deep Trench Spray Coating Final Presentation Karthik Vijayraghavan Mentor : Jason Parker 12/08/2010 1

Sprays a resist mixture using an ultrasonic nozzle. Typical droplet diameter ~ 20um Low spin speeds (30rpm – 60rpm) Resist thickness is typically 10um+. Lower thickness possible if ▫Shallow features, or ▫Deep features but large areas to fill resist Can be used to protect sidewalls and corners with resist Uses relatively little resist material Both, planar and conformal coatings possible using different nozzles (‘vortex’ and ‘accumist’) 12/08/ Introduction – EV101 Spraycoater DE10 Corner Sidewall (250um deep) DE10

Obtain a uniform coat of photoresist with thickness < 3µm in the region of interest at the bottom of a 350µm deep 350µm x 650µm DRIE trench coated with silicon nitride Thickness variation < 0.5µm Expose test pattern in ASML using the MSI patch to test resolution limits Starting recipe was Pierres Ponce’s P44 12/08/ Objectives 350µm X-Section View 650µm 350µm 60µm Top View

Wafer Preparation Fusion bond two R-prime wafers using the teflon jig with 0.5um oxide on handle. Exact procedure in wiki ASML alignment marks Deposit 3um LTO and pattern trenches Sts2 DRIE etch through top wafer 12/08/ Strip masking oxide and BOX in 6:1 BOE. Deposit nitride Before coating 20min in 9:1 piranha Followed by HMDS prime in YES oven

Parameters Explored Resist mixture consists of: ▫Photoresist SPR (4.8% %) ▫Low vapor pressure solvent Ethyl Lactate (25% - 45%) ▫High vapor pressure solvent MEK (remaining) Resist mixture dispense rate (3ul/s – 15ul/s) Nozzle pressure (300mbar – 900mbar) Number of passes (5 – 15) Velocity profile Heated chuck was used and set at 75C Total of 91 experiments exploring different combination of parameters. All results available on wiki 12/08/2010 5

N21 9 ul/s 10 pass Repeatability Experimental results are repeatable 12/08/ % Resist 25% LVP K02 12 ul/s 450 mbar 10 pass R06 12 ul/s 450 mbar 10 pass 7.7% Resist 25% LVP K01 9 ul/s 750 mbar 10 pass R08 9 ul/s 750 mbar 10 pass R14 9 ul/s 750 mbar 10 pass 5% Resist 45% LVP N13 9 ul/s 450 mbar 10 pass 450 mbar

Effect of Pressure Higher pressure improves uniformity and causes less pooling of resist at the bottom of trench 12/08/ ul/s 100 mbar 10 pass R01 5% Resist 45% LVP 5% Resist 25% LVP 11.5% Resist 44.6% LVP N15 12 ul/s 300 mbar 10 pass N23 12 ul/s 450 mbar 10 pass R02 9 ul/s 450 mbar 10 pass R03 9 ul/s 750 mbar 10 pass DE21 9 ul/s 100 mbar 15 pass DE24 9 ul/s 450 mbar 5 pass DE22 15 ul/s 450 mbar 5 pass

Velocity Profile 12/08/ Nga N Pham et al 2005 “Spray coating of photoresist for pattern transfer on high topography surfaces”, J. Micromech. Microeng. 15 pp Center Edge Area to be coated is higher at edge as compared to center. Hence, velocity needs to be adjusted to obtain uniform coating thickness Velocity profile can be scaled to increase or decrease overall time per pass Scaling also changes dispense rate if thickness is to be kept constant Slow passes lead to less rough films. But can cause resist pooling due to large quantity of resist being dispensed

Zygo Results (Jason) Zygo measurements on select samples. Full results on wiki Samples coated with 300A of Aluminum Surface roughness for above sample: ▫Ra = 0.223um ▫RMS = 0.271um 12/08/ N4

Recipe Used For ASML Exposure Testing Resist Mix : 5% SPR 220-7, 35% Ethyl Lactate, 60% MEK Dispense rate: 9ul/s, Pressure: 600mbar, Passes: 12 12/08/ Center Mid Edge G11

Deep Trench Lithography With ASML ASML in ‘normal’ mode ▫Cannot apply focus offsets of more than 30um ▫Global leveling is done at three points which are not user controllable. If deep features are present the wafer can get rejected ASML in special ‘MSI’ patch mode ▫Gives user control of level sensor locations. However need large area (10 x 10mm) Deep trench lithography possible if 3 large 10 x 10mm squares (GL openings) are etched to the same level as features to be exposed GL openings need to have low roughness 12/08/

Exposure Testing with ASML 4um features could be resolved in the large 10mm x 10mm trenches up to 1mm from the trench walls Dose of 150mJ and 2min development cleared some of the features and not others. Over exposed wafer second time with 250mJ to clear resist from all areas Resist couldn’t be cleared from smaller 350um x 650um trenches even after high energy dose (700mJ) Manual development in Headway for 2min – 5min 12/08/ um 12um

Conclusions Developed a spraycoat recipe for coating resist in 350x650 wide and 350um deep cavities Final recipe ▫Resist mix: 5% SPR 220-7, 35% Ethyl Lactate and 60% MEK ▫Dispense rate: 9ul/s ▫Pressure: 600 mbar ▫Passes: 12 Resist thickness in the central 100um x 100um area at the bottom of trench 2.7um ± 0.3um Tested recipe for deep trench lithography applications with ASML and was able to resolve 4um features in large areas 12/08/

Acknowledgements Jason Parker, Pierre Ponce, J Provine Makoto Nakamura, Linda Ohara, Ping Ding, Vinny Pici Mahnaz Mansourpour, Mary Tang 12/08/