 Designing CU – One FF per State Method  5 Transformation Rules  Transformation Process  Microprogrammed Control Unit

 1 FF is assigned to each state  At any one time, only one FF is high, the rest contain 0 (low)  The design starts with the ASM chart, and replaces 1.State Boxes with flip-flops, 2.Scalar Decision Boxes with a demultiplexer with 2 outputs, 3.Vector Decision Boxes with a (partial) demultiplexer 4.Junctions with an OR gate, and 5.Conditional Outputs with AND gates.

 Each state box transforms to a D Flip-Flop  Entry point is connected to the input.  Exit point is connected to the Q output.

 Each Decision box transforms to a Demultiplexer  Entry points are "Enable" inputs.  The Condition is the "Select" input.  Decoded Outputs are the Exit points. DEMUX EN A0 D0 D1 Entry X Exit 0 Exit 1

 Entry point is Enable input.  The Condition is the "Select" input.  Demultiplexer Outputs are the Exit points.  The Control OUTPUT is the same signal as the exit value.

 Each Decision box transforms to a Demultiplexer  Entry point is Enable inputs.  The Conditions are the Select inputs.  Demultiplexer Outputs are the Exit points.

 Where two or more entry points join, connect the entry variables to an OR gate  The Exit is the output of the OR gate

1.Replace each state with D FF (IDLE, MUL0 & MUL1) 2.Replace decision boxes with demultiplexer, decision variable as its selection input (G & Z), Q 0 use rule 3 as it’s condition goes to the same state 3.Each junction is replaced by an OR gate. 4.For output refer back to CU Table : Table 8.1 Initialize = IDLE · G Load = MUL0 · Q0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1

1.State Box  D FF 2.Decision Box  Demux 3.Junction  OR gate 4.Conditional  AND gate Corrections: Demux Z, D0 goes to MUL0 D1 goes to MUL1 Initialize = IDLE · G Load = MUL0 · Q0 Clear_C = IDLE · G + MUL1 Shift_dec = MUL1

 In processing each bit of the multiplier, the circuit visits states MUL0 and MUL1 in sequence.  By redesigning the multiplier, is it possible to visit only a single state per bit processed?  Remember the Alternative ASM  (try and do it yourself at home/hostel)

 Microprogrammed Control — a control unit with binary control values stored as words in memory.  Microinstructions — words in the control memory.  Microprogram — a sequence of microinstructions.  Control Memory — RAM or ROM memory holding the microinstructions.  Writeable Control Memory — RAM Memory into which microinstructions may be written

Fig. 8.17: Morris Mano, pg 391 Control Memory is assumed to be a ROM which all control microprograms are permanently stored. The control address register (CAR) specifies the add. of the microinstructions. The control data register (CDR), which is optional, may hold the microinstructions currently being executed by the datapath and the CU When a microinstruction is executed, the next-address generator (NAG) produces the next address. The NAG + CAR is sometimes called a microprogram sequencer.

 Memory Basics ◦ Random Access Memory (RAM)  Write and Read Operations  Properties of Memories ◦ SRAM  Integrated Circuits  Coincident Selection  Array of SRAM ICs  Constructing SRAM for extended Address Line  Constructing SRAM for extended Word bits