Design of a 300 Mbps Unified 3G/4G Turbo Decoder Using High-Level Synthesis Primary Author: Sandeep RK Secondary Author: Pankaj Saxena Company/Organization:

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Presentation transcript:

Design of a 300 Mbps Unified 3G/4G Turbo Decoder Using High-Level Synthesis Primary Author: Sandeep RK Secondary Author: Pankaj Saxena Company/Organization: Broadcom

ISCUG – India SystemC User Group 2 Agenda MotivationMotivation Turbo DecoderTurbo Decoder ChallengesChallenges MethodologyMethodology ResultsResults HLS AdvantagesHLS Advantages RecommendationsRecommendations

ISCUG – India SystemC User Group 3 Motivation Scalable architectureScalable architecture Should support the following throughputs:Should support the following throughputs: 3G – 3.6, 7.2, 14, 21, 42, 84, 168 Mbps3G – 3.6, 7.2, 14, 21, 42, 84, 168 Mbps LTE – 75, 100, 150, 300 MbpsLTE – 75, 100, 150, 300 Mbps Minimum area and powerMinimum area and power Establish high-level synthesis (HLS) flowEstablish high-level synthesis (HLS) flow

ISCUG – India SystemC User Group 4 3G/LTE Turbo Encoder Ref:Ref: 3GPP TS version Release 10

ISCUG – India SystemC User Group 5 Challenges Address conflicts in 3G interleaverAddress conflicts in 3G interleaver –>5000 block sizes in 3G. –Results in nondeterministic throughput. –Modeling is required to choose the architecture. Odd block sizes in 3GOdd block sizes in 3G Interleaved address generation in 3GInterleaved address generation in 3G

ISCUG – India SystemC User Group 6 Turbo Decoder 300 Mbps for LTE, and 168 Mbps for 3G300 Mbps for LTE, and 168 Mbps for 3G Eight parallel Radix4 MAP decodersEight parallel Radix4 MAP decoders Up to eight full iterationsUp to eight full iterations CRC-based early terminationCRC-based early termination

ISCUG – India SystemC User Group 7 Block Diagram

ISCUG – India SystemC User Group 8 Methodology Design and test bench: SystemCDesign and test bench: SystemC –Each block in one or two CThreads Verification: Bit matching with reference vectorsVerification: Bit matching with reference vectors HLS tool: Forte CynthesizerHLS tool: Forte Cynthesizer RTL synthesis: Design CompilerRTL synthesis: Design Compiler Single test bench for performance evaluation, RTL, and netlist simulationsSingle test bench for performance evaluation, RTL, and netlist simulations

ISCUG – India SystemC User Group 9 Results ~60% area reduction compared to separate 3G & 4G decoders.~60% area reduction compared to separate 3G & 4G decoders. Area is reduced by 10% due to HLS.Area is reduced by 10% due to HLS. ~50% is memory.~50% is memory. Area is reduced proportional to throughput due to scalable architecture.Area is reduced proportional to throughput due to scalable architecture. BER remains the same.BER remains the same. Throughput requirements are met for both 3G & LTE.Throughput requirements are met for both 3G & LTE.

ISCUG – India SystemC User Group 10 HLS Advantages Architecture explorationArchitecture exploration Process technology independent designProcess technology independent design Readily available interfacesReadily available interfaces Built-in math operations like saturation, rounding, etc.Built-in math operations like saturation, rounding, etc. Smaller areaSmaller area Easy to work with memoriesEasy to work with memories Shorter design cycleShorter design cycle

ISCUG – India SystemC User Group 11 Recommendations Control signals should flow along with the data path. Adds flexibility to synthesize designs at different frequencies. Reset values to all variables.Reset values to all variables. SystemC assigns 0 by default.SystemC assigns 0 by default. Group the inputs/outputs having the same delay requirements.Group the inputs/outputs having the same delay requirements. Avoid multicycle paths.Avoid multicycle paths. Use consistent coding style.Use consistent coding style. –Input registering versus output registering.

ISCUG – India SystemC User Group 12 Recommendations (continued) Memory access delays are different in SystemC and RTL. Need a scheme to avoid SystemC/RTL mismatch.Memory access delays are different in SystemC and RTL. Need a scheme to avoid SystemC/RTL mismatch. Avoid write-through conditions in dual-port memories.Avoid write-through conditions in dual-port memories. Be careful about simultaneous read/write operations in single-port memories.Be careful about simultaneous read/write operations in single-port memories.

ISCUG – India SystemC User Group 13 Questions?

14 Thank you!