Status report 2011/1/21 Atsushi Nukariya

Progress ・ Progresses are as follows. 1. I created wave form which Fusayasu-san showed. → Rearrange design. → Change clock frequency. → Add another clock. 2. Chip test.

Wave form (1) ・ Requested wave form is as follows. → This is wave form about LSI, not internal on FPGA. → RCLK is stopped 1 RCLK when “EMPTY (0x200000)” is sent. → To stop RCLK, it needs clock whose frequency is two times as much as RCLK’s frequency. → Current design can’t implement this behavior. → Rearrange design. Input Data RCLK RADDRESS FIFOSEL

Wave form (2) ・ Current design is as follows. MCLK(10MHz) RCLK(20MHz) HCLK(100MHz) Clock Generator Signal Processor Crystal Unit SiTCP 10 MHz RCLK Controller GEMFE2 Enable signal

Wave form (3) ・ New design is as follows. → The Xilinx tools can’t make this, because number of DCM is limited to 1. Clock Generator Signal Processor Crystal Unit SiTCP 10 MHz RCLK Controller Clock Generator Enable signal GEMFE2 MCLK(10MHz) RCLK(20MHz) RCLKx2(40MHz) HCLK(100MHz)

Wave form (4) ・ Revised design is as follows. → The Xilinx tools implements this design with no problem. Clock Generator Signal Processor Crystal Unit SiTCP 10 MHz RCLK Controller MCLK Generator Enable signal GEMFE2 MCLK(5MHz) RCLK(10MHz) RCLKx2(20MHz) HCLK(50MHz)

Wave form (5) ・ Created data is as follows. ( Simulation. ) FIFOSEL DBuffer Output FIFOx3 Output SiTCP Input Counter Data Input RCLK_C HCLK RCLKx2 RCLK MCLK

Wave form (6) ・ Created data is as follows. ( Simulation. ) → This wave form is corresponds to wave form which Fusayasu-san showed.

Chip Test (1) ・ We searched value which chip works correctly. ・ This is wave form from Logic-Analyzer when RCLK frequency is 2 MHz. ( In first design, RCLK frequency is 10 MHz. )

Chip Test (2) ・ When RCLK frequency is 4 MHz, there are crosstalk and noise.

Chip Test (3) ・ When RCLK frequency is 10 MHz, most of output data are crosstalk and noise. → If chip works correctly, there is signal at RADDRESS 0 and 1 only. → More detail research is in progress.