1. University of Malta ICECS 2010 Terence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef Presented by: Terence Zarb Department of Microelectronics and Nanoelectronics

2.  Aims of Research  Background Theory ◦ Operation of a GPS Receiver  Design ◦ Hardware Modules ◦ Satellite Signal Modulation Model  Results ◦ One Satellite Transmission ◦ Multiple Satellite Transmissions ◦ Noise Performance  FPGA Usage 2

3.  Design of various digital signal processing and communication blocks which form an integral part of a typical L1-band C/A-code GPS receiver Using synthesisable VHDL code  Design of a GPS satellite signal modulation model  Noise performance analysis of the designed baseband processor 3

4. GPS main segments 4

5.  A GPS receiver is made up of 3 main parts: Analogue front-end chip Digital baseband processor Dedicated CPU 5

6.  Baseband processor: demodulates navigation data coming from different satellites Demodulation = acquisition + tracking  Acquisition: Generate local replica of incoming signal:  carrier replica + C/A-code replica Synchronise the local and incoming signals  determine the code phase and carrier Doppler frequency Down convert the incoming signal to baseband and cross-correlate the result with the local C/A-codes 6

7.  Tracking: Maintains lock between the local and incoming signals Carrier tracking loop using a Phase-Locked Loop (PLL) Code tracking loop using a Delay-Locked Loop (DLL) 7 Baseband Processing

8.  The baseband processor hardware modules are designed using synthesisable VHDL code  The GPS satellite signal modulation model is designed using MATLAB ® Simulink 8 System Design

9.  Carrier Generator: Front-end chip used is the GP2015 which down converts the L1 frequency to 4.309 MHz IF IF bandwidth = 2.046 MHz; f S = 5.102 MHz Aliasing occurs and the IF frequency is further down converted to 793 kHz Local carrier = 2.4 sin (2π(793k)t) 9 Carrier Quantisation

10. 10  Carrier Samples: Carrier Samples (circles) and Envelope (dotted) vs. Sample Number Sample Number Magnitude

11.  Baseband Mixer: Mixes incoming 2-bit digitised IF signal with local carrier Each baseband sample requires 3-bit to be represented 11 2-bit combinations of digitised IF 3-bit combinations of baseband mixed signal

12.  C/A-Code Generator: Generates the C/A-codes of all 24 satellites in parallel at a rate of 1.023 MHz 12

13.  Four-channel Parallel Correlator: Correlates the baseband signal with the local C/A-codes of four satellites simultaneously Corr(△) =∑b(n) ⨉c(n –△); 0≤△≤1022 13 One-Channel Parallel Correlator Baseband Signal 1023-bit shift register 1.023 MHz clock DQDQDQDQDQ C/A-Code Generator ∑ ∑∑∑∑ S0S0 S1S1 S2S2 S3S3 S 1022

14.  Comparator: Selects four satellites for data demodulation and determines their correct code phase delays Controls which four satellites are processed simultaneously by the correlator Accumulation interval = 2 ms  Navigation Data Demodulator: 14 Determination of navigation data bits Correlation Polarity after the first 10 ms interval Correlation Polarity after the second10 ms interval Navigation Data Bit Positive No change (1) Positive NegativeTransition from ‘1’ to ‘0’ Negative PositiveTransition from ‘0’ to ‘1’ Negative No change (0)

15.  Satellite Signal Modulation Model 15

16.  The correct functionality of each module was verified through various simulations  VHDL modules were tested using ModelSim®  Satellite signal modulation model was tested using MATLAB® Simulink Simulation tool  Evaluation setup: Bottom-up approach Tests for one satellite transmission Tests for multiple satellite transmissions Analyse noise performance of baseband processor 16

17.  BPSK IF Signal generation for one satellite: 17

18.  Correlation results for one satellite (SV 0) transmission: 18

19.  Correlation results for one satellite (SV 0) transmission: 19

20.  Results for multiple satellite transmissions: 20

21.  Noise Performance: 21

22.  Noise Performance: 22

23. 23 ModuleInferred Hardware Baseband Mixer and Carrier Generator 1 13-bit up counter1 13-bit Comparator 5102 ⨉ 2 bits LUT C/A-code Generator 5 registers (21 D-type flip-flops) 1 2-input XOR gate 1 6-input XOR gate Correlator 4,093 adders/subtractors 8,188 comparators 4,105 registers (61,403 D- type flip-flops) Comparator 8 adders /subtractors62 comparators 1,062 registers (14,759 D- type flip-flops) 1 10-bit up counter 5 MUXs Navigation Data Demodulator 1 6-bit register (6 flip-flops)

24.  Correlation between incoming and local codes is reduced when:  Number of parallel transmissions is increased  SNR is reduced  Minimum SNR value that processor can tolerate is -10 dB when gain control is adopted  The front-end AGC is crucial in the performance of the baseband processor  If no gain control is adopted, minimum SNR that the receiver can tolerate is greater than -10 dB 24

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