1. Status report 2011/7/15 Atsushi Nukariya

2. Progress Progresses are as follows. 1. GEMFE2 Chip -> The signal is seen. 2. FPGA -> Data format is changed. 3. Software -> Revise.

3. GEMFE2 Chip Fusayasu-san created temporary verilog code. -> The ADC value is output correctly. -> Image processing is next target.

4. FPGA -1- ・ Chip can read input data correctly. -> Output data format from FPGA is changed. EMPTY (0x200000**) DATA (0x??????**) x8 Next Chip EMPTY (0x200000**) DATA (0x??????**) x8 Token (0x7fffff**) Next Chip

5. FPGA -2- SiTCP clock is same as RCLK. -> The speed is slow compared to the amount of input data. OSCPLL MCLK(1.25MHz) RCLK(2.5MHz) RCLKx2(5MHz) HCLK(12.5MHz) SiTCPCLK(6.25MHz)

6. FPGA -3- Data Generator Data Ctrl FIFO SiTCP FIFO SiTCP ① ② ③

7. FPGA -4- ① ③ ②

8. Software Analysis will be started after 0x7fffffff is received. Channel, FIFO and Chip number are always checked.

9. Source code FPGA http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_fpga/ Debug Software http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_debug_software/ Script http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_scripts/ Image Processing Software http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_software/