HVPS Configurations JEM EUSO Balloon Pierre Prat 17/09/2012.

Slides:



Advertisements
Similar presentations
Supervisory Control & Data Acquisition DAQ Networking.
Advertisements

Service Board Production Test Rafael Nobrega LHCb Roma1.
ECE 371 Unit 13 - Part 1 Serial Peripheral Interface (SPI)
Peripherals and their Control An overview of industrially available “peripheral devices” Some ideas for Laboratories and Quiz / Exam questions.
Serial Communication Buses: I 2 C and SPI By Brody Dunn.
ITASK Final Presentation May 3, 2007 EE 296 Kazuki Morishita Archimedes.
University of Kansas EPS of KUTEsat Pathfinder Leon S. Searl April 5, 2006 AE256 Satellite Electrical Power Systems.
Guitar Effects Processor Critical Design Review October, 07, 2003 Groups Members: Adam Bernstein Hosam Ghaith Jasenko Alagic Matthew Iyer Yousef Alyousef.
Serial Peripheral Interface (SPI)
CR1000s are only one part of a data acquisition system. To get good data, suitable sensors and a reliable data retrieval method are required. A failure.
SPISPI Term Dr Abdelhafid Bouhraoua Term Dr Abdelhafid Bouhraoua.
Aztec PC Oscilloscope Michael Mason Jed Brown Josh Price Andrew Youngs.
CR1000s are only one part of a data acquisition system. To get good data, suitable sensors and a reliable data retrieval method are required. A failure.
HK & LVPS for EUSO –TA / -Balloon G. Medina-Tanco, L. Santiago, H. Silva Lopez, F. Trillaud, C. Lopez, J. Rojas, A. De la Cruz, S. Guerrero, G. Leon.
EtherCAT (Beckhoff) for advanced LIGO
End of phase A meeting CNES (Toulouse) 2/02/2012 Ph. Gorodetzky APC - Paris Diderot1 High Voltage power supplies HV Switches Design: J. Szabelski, J. Karcmarczyk,
- Grounding - Harness Shielding - PDM Electrical Architecture - DP Electrical Architecture EUSO-BALLOON DESIGN REVIEW, , CNES TOULOUSE Pierre.
Welcome to Workshop 88’s Tiny85 Class Please download Tiny core libs from: (for Arduino 1.0, not 1.5!) Unzip and.
- Battery Pack Technical Specifications - Battery Pack Design Descriptions - Battery Pack Connection Diagram - Battery Pack Architecture EUSO-BALLOON DESIGN.
Serial Peripheral Interface (SPI) Bus. SPI Bus There is no official specification for the SPI bus. It is necessary to consult the data sheets of the devices.
CCD Clocking and Biasing CABAC_0 : Design Test_0 : Design Pierre Antilogus (from a Hervé Lebbolo’s talk) BNL, Raft Electronic Workshop January 25 th 2012.
Footswitch Controller – Hardware System View – Level 0.
- Where are the entry points of the instrument - Physical External links - Overview of the External Interfaces - Status - Conclusion EUSO-BALLOON DESIGN.
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
Recommendation and actions EUSO EUSO-BALLOON FLIGHT REVIEW, , CNES TOULOUSE Guillaume Prévôt APC, Paris Wrap up previous actions.
Basic I/O Interface A Course in Microprocessor
Calorimeter upgrade meeting - Wednesday, 11 December 2013 LHCb Calorimeter Upgrade : CROC board architecture overview ECAL-HCAL font-end crate  Short.
Chicago Meeting, /8/2015K.-H. Sulanke, DESY1 Digital Camera Trigger Status May 2013 K.-H. Sulanke DESY.
Embedded System Design Laboratory October 4, 2002Stanford University - EE281 Lecture #3#1 Lecture #3 Outline Announcements AVR Processor Resources –UART.
University of Calcutta CBM 1 ROC Design Issues Dr. Amlan Chakrabarti, Dr. Sanatan Chattopadhyay & Mr. Suman Sau.
CaRIBOu Hardware Design and Status
TRIO-CINEMA 1 UCB, 2/08/2010 Instrument Interface Board Dorothy Gordon CINEMA - EE Team Space Sciences Laboratory University of California, Berkeley.
1 Chap. 3 Interface. 2 Interface  Physical connection between node and transceiver  Network interface card (NIC)  Physical connection between transceivers.
1 Outline Firmware upgrade of the HV_LED_DAC boards. HV Status Bits board. Status of the board integration into the LHCb TFC system. CALO HV system and.
HOUSEKEEPING HK at Balloon-EUSO 10 th JEM-EUSO meeting from December 5 th to 10 th at RIKEN, Tokyo By G. Medina-Tanco*, A. Zamora, L. Santiago Cruz**,
EC_ASIC drawing (1) ASIC BASIC FASIC D 68 pi ns ASIC A 68 pi ns ASIC C ASIC E 120 pins ABCDEF 68 pi ns 68 pi ns 68 pi ns 68 pi ns.
TCSP Presentation #3 Team 14 SPOT DASH. Schematics 3 Pages 3 Pages Page 1: Buttons, LEDs, sensors related circuits Page 1: Buttons, LEDs, sensors related.
Microprocessor based Design for Biomedical Applications MBE 3 – MDBA XI : Project Outlooks.
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
Network and Systems Laboratory nslab.ee.ntu.edu.tw se.
FE-I4 Test Setup Hardware Needs: Boards & Interfaces March 1 st 2010, Marlon Barbero.
Mar. 18, 2009 HAPD ASIC Status Super KEKB Meeting 1 S.Nishida (KEK) S. Nishida HAPD ASIC Status Super KEKB Meeting Mar. 18, 2009 KEK.
HK-status. RS422 (diff) RS232 SPI Trigger rate Analog(V,T) >=4 Analog(V,T)
1/12/2010 R. CIARANFI 1 NEW NINO BOARD FOR RICH OLD AND NEW LOGISTIC NEW BOARD DESCRIPTION NEW MODULARITY 32 CH NEW FORM FACTOR FRONT END AREA AND DAQ.
Kay Rehlich xTCA RT2012 MicroTCA.4 Timing Distribution and Power Supply Issues.
Revised: Aug 1, ECE263 Embedded System Design Lessons 27, 28 Serial Peripheral Interface.
Assumptions: Cockcroft-Walton photomultiplier bases are the same for all ECAL sections Digital to analog converters are installed on the distribution boards.
PSI - 11 Feb Status of the electronic systems of the MEG Experiment.
0-10V Ballast Dimmer HDL-MRDA HDL-MRDA channel 10A DC0 - 10V output module is a multifunction control module. It has 6 channel relay.
PowerBench Programmable Power Supply Dror Lazar Moran Fishman Supervisor: Boaz Mizrahi Winter Semester 2009/10 HS DSL.
Planning of the EUSO-BALLOON project Sylvie Dagoret-Campagne on behalf of the JEM-EUSO collaboration, EUSO-BALLOON project manager LAL/France EUSO BALLOON.
T HE PDM INTEGRATION P. Barrillon (LAL) & G. Prévôt (APC) On behalf of the PDM crew (Simon, Lech, Philippe, Sylvie B) EUSO-SPB/MiniEUSO progress meeting,
DAQ ELECTRONICS 18 March 2015MEG Collaboration Meeting, Tokyo Stefan Ritt.
第 三 章 矿物在正交偏光镜下的 均质性、非均质性.
DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011.
The Slow Control System of the HADES RPC Wall Alejandro Gil on behalf of the HADES RPC group IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain IEEE-RT2009.
Michel DUPIEUX IRAP Progress Meeting LAL 02/03/ EC interface with PDM.
DOM Electronics (Digital Optical Module) 1 WPFLElectronics PPMDOM ElectronicsF. Louis.
Pierre PRAT Progress the Michel DUPIEUX.
Backplanes for Analog Modular Cameras EVO meeting. March 14 th,
EC electronic status. Outline Reminders History EC-front unit status EC_ASIC status What next ? 2.
DU power Principle diagram OM inventory Conversions VEOC behavior DU to network Pending issues mPMT-Bar.
Not So Deep Blue The original Deep Blue. LED chess board Track movements of all pieces Show possible moves Track game time Detect piece movement -Magnets/Reed.
CALICE Readout Board Front End FPGA
Serial Communication Buses: I2C and SPI
High-Voltage Supply Requirements Review
Chapter 8 Data Acquisition
EVLA MONITOR & CONTROL CDR
Wireless Autonomous Trolley
Radio Interface Board Status
Presentation transcript:

HVPS Configurations JEM EUSO Balloon Pierre Prat 17/09/2012

HVPS I/F configuration versions Version 1: page 3 (C-W gain commands provided by PDM_Board) – HVPS-1: HK SPI I/F + LVDS PDM_Board I/F + 28V 3.3V DC/DC CV – HVPS-2: 9 C-W Version 2: page 4 (C-W gain commands provided by PDM_Board) – HVPS-1: 3 C-W + HK SPI I/F + LVDS PDM_Board I/F + 28V 3.3V DC/DC CV – HVPS-2: 6 C-W Version 3 : page 5 (Internal C-W gain commands by D12 current measurement) – HVPS-1: 3 C-W + HK SPI I/F + 28V 3.3V DC/DC CV + FPGA/comparators/3 D12 current measurements – HVPS-2: 6 C-W + 6 D12 current measurements Version 4 : page 6 (Internal C-W gain commands by D12 current measurement) – HVPS-1: 3 C-W + 28V 3.3V DC/DC CV + FPGA/comparators/3 D12 current measurements – HVPS-2: 6 C-W + 6 D12 current measurements – HVPS-3: HK SPI I/F

D-Sub 37 M HVPS-2 HK BAT_RET (P) 28V_BAT (P) GND_28V (S) GND_3.3V (S) 28V (S) 3.3V (S) GND_M HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome the CW and switch system GND_M V STATUS ON/OFF CN9 CN4 CN3 CN DAC 6 Differential signals (LVDS) ( x2 = 18 wires) between HK and HVPS1 4 differential transmitters 2 differential receivers 22 CS_DAC CS_IO HVPS-1 MISO MOSI SCK MOSI 9 analog signals 9 bidirectional signals 9 status signals I/O expander s 4 differential transmitters 4 differential receivers PDM Board 16 wires MISO Interrupt SCK Interrupt HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : version 1 3 D-Sub 9 F Micro-D 9 F D-Sub 15 F Micro-D 9 F D-Sub 37 F D-Sub 15 M Micro-D 9 M 9 C-W D-Sub 9M D-Sub 9 F D-Sub 9M BATTERY 4 differential signals (LVDS) between PDM Board and HVPS-1 x 2 = 8 wires

D-Sub 37 M HVPS-2 HK 1 2 BAT_RET (P) 28V_BAT (P) GND_28V (S) GND_3.3V (S) 28V (S) 3.3V (S) GND_M HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome 6 C-W and switch system GND_M V STATUS ON/OFF CN9 CN3 CN differential signals (LVDS) between PDM Board and HVPS-1 x 2 = 8 wires 9 DAC 6 Differential signals (LVDS) ( x2 = 18 wires) between HK and HVPS1 4 differential transmitters 2 differential receivers 22 CS_DAC CS_IO HVPS-1 MISO MOSI SCK MOSI 6 analog signals 6 bidirectional signals 6 status signals I/O expander s 4 differential transmitters 4 differential receivers PDM Board 16 wires MISO Interrupt SCK Interrupt HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : version 2 4 D-Sub 9 F Micro-D 9 F D-Sub 15 F Micro-D 9 F D-Sub 37 F D-Sub 15 M Micro-D 9 M 6 C-W D-Sub 9M D-Sub 9 F D-Sub 9M BATTERY 3 C-W CN4 CN3 CN2 CN4 CN9 6 x 14 HV lines 3 x 14 HV lines STATUS 3 ON/OFF V GND_M

D-Sub 37 M HVPS-2 HK 1 2 BAT_RET (P) 28V_BAT (P) GND_28V (S) GND_3.3V (S) 28V (S) 3.3V (S) GND_M HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome 6 C-W and switch system GND_M V STATUS ON/OFF CN9 CN3 CN2 9 DAC 6 Differential signals (LVDS) ( x2 = 18 wires) between HK and HVPS1 4 differential transmitters 2 differential receivers CS_DAC CS_IO HVPS-1 MISO MOSI SCK MOSI 6 analog signals 6 bidirectional signals 6 status signals I/O expander s 4 differential receivers MISO Interrupt SCK Interrupt HVPS-1 - HVPS-2 - HK Interface Synoptic : version 3 5 D-Sub 9 F D-Sub 15 F D-Sub 37 F D-Sub 15 M 6 C-W D-Sub 9M D-Sub 9 F D-Sub 9M BATTERY 3 C-W V 3 ON/OFF 3 STATUS CN4 CN3 CN2 CN4 CN9 6 x 14 HV lines 3 x 14 HV lines Comparators + FPGA 4 CN status 6 I-D12 analog signals 3 I-D12 analog signals x 3 GND_M

D-Sub 15 M HVPS-2 HK 1 2 BAT_RET (P) 28V_BAT (P) GND_28V (S) GND_3.3V (S) 28V (S) 3.3V (S) GND_M HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome 6 C-W and switch system GND_M V STATUS ON/OFF CN9 CN3 CN2 9 DAC 6 Differential signals (LVDS) ( x2 = 18 wires) between HK and HVPS1 4 differential transmitters 2 differential receivers CS_DAC CS_IO HVPS-3 MISO MOSI SCK MOSI 6 analog signals 6 bidirectional signals 6 status signals I/O expander s 4 differential receivers MISO Interrupt SCK Interrupt HVPS-1 - HVPS-2 – HVPS-3 - HK Interface Synoptic : version 4 6 D-Sub 9 F D-Sub 15 F D-Sub 15 M 6 C-W D-Sub 9M D-Sub 9 F D-Sub 9M BATTERY 3 C-W V 3 ON/OFF 3 STATUS CN4 CN3 CN2 CN4 CN9 6 x 14 HV lines 3 x 14 HV lines Comparators + FPGA 4 CN status 6 I-D12 analog signals 3 I-D12 analog signals x 3 GND_M D-Sub 15 M D-Sub 15 F D-Sub 15 M D-Sub 15 F 3.3V (S) GND_3.3V (S) HVPS-1 D-Sub 25 M D-Sub 25 F