8 085Microprocessor

Temp Reg (8) Accumulator (A reg) Flag flip flops(8) Instruction Register (8) Arithmetic Logic Unit ALU Instruction Decoder and Machine cycle encoding B reg (8) D reg (8) C reg (8) H reg (8) E reg (8) L reg (8) Stack Pointer (16) Program Counter (16) Incrementer/ Decrementer address Latch (16) Address Buffer (8) Address/data Buffer (8) CLK out CLK Timing & Control GEN CONTROL STATUS DMA RESET Ready RD WR ALE S 0 S 1 IO/M HOLD HLDA RESET IN RESET OUT Serial I/O control SOD SID Interrupt Control INTR INTA RST 5.5 RST 6.5 RST7.5 TRAP Register Set A 15 – A 8 AD 7 – AD 0 Address bus Address/Data bus 8-bit internal data bus 8085 ARCHITECTURE (8) Multiplexer X1 X2

Temp Reg (8) Accumulator (A reg) Flag flip flops(8) Instruction Register (8) Arithmetic Logic Unit ALU Instruction Decoder and Machine cycle encoding B reg (8) D reg (8) C reg (8) H reg (8) E reg (8) L reg (8) Stack Pointer (16) Program Counter (16) Incrementer/ Decrementer address Latch (16) Address Buffer (8) Address/data Buffer (8) CLK out CLK Timing & Control GEN CONTROL STATUS DMA RESET Ready RD WR ALE S 0 S 1 IO/M HOLD HLDA RESET IN RESET OUT Serial I/O control SOD SID Interrupt Control INTR INTA RST 5.5 RST 6.5 RST7.5 TRAP A 15 – A 8 AD 7 – AD 0 Address bus Address/Data bus (8) Timing Circuit Fetching and Decoding of instructions EXECUTION UNIT Multiplexer X1 X2

Timing & Control Timing Circuit: CLK – 5 MHz X1, X2 (Input) :Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. CLK (Output) : Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. RESET IN (Input) Reset sets the Program RESET OUT (Output) Indicates CPU is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.

CONTROL READY (Input): If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. RD,READ: indicates the selected memory or I/0 device is to be read and that the DataBus is available for the data transfer. WR,WRITE: indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address. IO/M: IO/M indicates whether the Read/Write is to memory or l/O

STATUS: S1 S0 OOHALT 01WRITE 10READ 11FETCH

DMA (Direct Memory Access): HOLD (Input) HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. HLDA (Output) HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. Memory

Register Set: Accumulator: It is the processor register. At least one operand is definitely present in accumulator B reg (8) D reg (8) C reg (8) H reg (8) E reg (8) L reg (8) Instruction Register (8) Instruction Decoder and Machine cycle encoding Stack Pointer (16) Program Counter (16) Incrementer/ Decrementer address Latch (16)

D7D7D7D7 D6D6D6D6 D5D5D5D5 D4D4D4D4 D3D3D3D3 D2D2D2D2 D1D1D1D1 D0D0D0D0 SZACPCY Flag / Status bits/PSW/Program Status Word Flag flip flops(8) Arithmetic Logic Unit ALU

Serial I/O control SOD SID Interrupt Control INTR INTA RST 5.5 RST 6.5 RST7.5 TRAP Priority of interrupts: 1.TRAP (Non Maskable) : occurs at completion of each instruction. 2.RST RST RST These are restart interrupts 5. INTR 5 interrupts for 8085: INTR, RST 5.5,6.5,7.5 and TRAP SID: Serial i/p data SOD: Serial out data

Pin Description: 5 volts Vcc Ground

Memory Organisation of 8085: 8085 has 16 bit address lines, through which it is possible to address 2 16 locations, i.e., up to 64 kilobytes or 64 KB locations. Each location is represented with an address of 16 binary bits or 4 hexadecimal digits. For example: a location’s address can be shown as or just in simple way as 1000 H. In these 64 KB locations each location can hold 8 bits or a byte in it as 8085 has an 8 bit data width. Note : 8085 can also work on 16 bit data by splitting it in to two 8 bit data.

T 1 T 2 T 3 T 4 T 5 T 6 ADDRESS DATA CLK A0-A15 ALE D0-D7

ADDRESSING MODES

1. Immediate Addressing Mode: Data is present in the instruction. Load the immediate data to the destination provided. Example: MVI R,data 2. Register Addressing Mode: Data is provided through the registers. Example: MOV Rd, Rs 3. Direct Addressing Mode: Used to accept data from outside devices/port 00H to store in the accumulator or send the data stored in the accumulator to the outside device/ port 01H. Example: IN 00H or OUT 01H 4. Indirect Addressing Mode: This means that the Effective Address iscalculated by the processor. And the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored.

Programming Model Of 8085 INSTRUCTION SET Data Transfer Instructions Arithmetic Instructions Logical Instructions Branching Instructions

Data Transfer Instructions: MOV  Move ; copy a data byte from a memory/ register MVI  Move Immediate data ; load a byte directly IN  Input from port ; Read a data byte from an input device OUT  Output to port ; Send a data byte to an output device HLT  halt ; Stop processing and wait NOP  No operation ; do not perfrom any operation Arithmetic Operations: ADD : addition SUB : subtract ADI : Add immediate SUI : Subtract immediate INR : Increment DCR : Decrement

Logical Instructions: ANA : AND operation ANI : AND immediate ORA : OR ORI : OR immediate XRA: X-OR XRI : X-OR immediate CMA: complement accumulator RL: Rotate Left RLC : Rotate Left Through Carry RR : Rotate Right RRC: Rotate Right Through carry

Branching Instructions: Uncondtional branch: JMP : Jump to the specific address CALL: Call a subroutine Conditional branch: JC : Jump on carry JNC: Jump on no carry JZ : Jump on zero JNZ : Jump on not zero RET : Return from a subroutine RETI : Return from a interrupt sub routine

A simple Program Load Accumulator and B registers with immediate values and ADD them Memory Address Instruction Binary/HEX code MVI A,#05 MVI B,#04 ADD A,B HLT

Instruction constitutes of OPCODE and OPERAND/s Instruction types One byte instruction Two byte instruction Three byte instruction One byte instruction: MOV A,B; in hexa form it is only shown as 3B H It means that MOV is written in hexa form as 3EH understood by the system and A and B are internal registers so no need to show any other specific representation for them. So the number of bytes this instruction needs is only 1 byte.

Two byte instructions: Ex: MVI A,#05 ; load accumulator with an immediate data called 5. Here A is internal register, so it doesn’t need any other representation MVI and 05 are shown in binary of HEXA form as 3E for MVI and 05 for 05(data) So this instruction needs 16 binary bits or 2 bytes Three byte instructions: Ex: jmp 2000 Here 2000 is some 16 bit address, it already has two bytes in it and JMP needs other representation as C3. So this instruction is of 3 bytes

A simple Program Load Accumulator and B registers with immediate values and ADD them Memory Address Instruction Binary/HEX code MVI A,#05 MVI B,#04 ADD A,B HLT E, 04 3E, ?????

T1T1 T2T2 T3T3 T4T4 T1T1 T2T2 CLK T3T3 HIGH ORDERADDRESS 20 LOW ORDERADDRESS 00 ALE 3E HIGH ORDERADDRESS 20 LOW ORDERADDRESS A 15 -A 7 A 7 -A 0 Data D7 –D0 RD FETCH & DECODE CYCLE EXECUTE CYCLE MVI A, 05

CONCLUSIONS: 8085 Devoloped by INTEL CORPORATION An 8 bit Microprocessor 16 bit address lines Memory represented upto 64 KB. 4 Addressing Modes

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