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Detailed Review of the 8085 Instruction Set.

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Presentation on theme: "Detailed Review of the 8085 Instruction Set."— Presentation transcript:

1 Detailed Review of the 8085 Instruction Set

2 Classification of Instructions
Based on the parameters Functionality Instruction Length Data Transfer Instruction 1 Byte instructions Arithmetic Instructions 2 Byte instructions Logical Instructions 3 Byte instructions Branching Instructions Control Instructions

3 The classification of 8085 instructions based on functionality:
Data transfer Instructions Arithmetic Instructions (ADD, SUB, INR, DCR) Logical Instructions (NOT, AND, OR, EXOR) Branching Instructions (JMP, CALL, RET) Control Instructions (NOP, HLT, DI, EI, RIM, SIM) Between registers Between memory location and a register Direct write to a register / memory Between I/O device and accumulator

4 The classification of 8085 Instructions based on length
One Byte Instructions: Includes both opcode and operand in the same byte Example Opcode Operand Hex Code MOV C,A 4F ADD B 80 CMA 2F

5 8085 Instruction Types Opcode Operand Hex Code MVI A, 07 3E, 07
Two Byte Instructions: First byte specifies opcode and second byte specifies operand Example Opcode Operand Hex Code MVI A, 07 3E, 07

6 8085 Instruction Types Opcode Operand Hex Code JMP 2085 C3, 85, 20
Three Byte Instructions: First byte specifies opcode and the following two bytes specifies address Example Note: Second byte is lower order address Third byte is higher order address Opcode Operand Hex Code JMP 2085 C3, 85, 20

7 Data Transfer Instructions
MOV MOV rd, rs MOV rd, M MOV M, rs MVI MVI rd, 8-bit data MVI M, 8-bit data LDA 16-bit address STA 16-bit address LDAX rp (B/D register pair) STAX rp LHLD 16-bit address SHLD 16-bit address LXI rp, 16-bit data (Load register pair immediate) XCHG (Exchange H-L with D-E)

8 Register contents before Execution Register contents after Execution
Example MOV A, B Instruction: Register contents before Execution 9A h 89 h A B Register contents after Execution 89 h A B Note: No flags are modified during the execution of data transfer instruction.

9 Register contents before Execution Register contents after Execution
Example MOV C, M Instruction: Register contents before Execution 9A h 8500h C HL Register contents after Execution C2 h C 8500h HL 84FF 7Ah 8500 C2h 8501 8502 45h F4h MEMORY 84FF 7Ah 8500 C2h 8501 8502 45h F4h MEMORY

10 Register contents before Execution Register contents after Execution
Example MVI B, 18h Instruction: Register contents before Execution 9A h B Register contents after Execution 18 h B

11 Register contents before Execution Register contents after Execution
Example LDA 2005h Instruction: Register contents before Execution 87 h A Register contents after Execution 45 h A 2003 7Ah 2004 C2h 2005 2006 45h F4h MEMORY 2003 7Ah 2004 C2h 2005 2006 45h F4h MEMORY

12 Register contents before Execution Register contents after Execution
Example STA 2005h Instruction: Register contents before Execution 87 h A Register contents after Execution 87 h A 2003 7Ah 2004 C2h 2005 2006 87h F4h MEMORY 2003 7Ah 2004 C2h 2005 2006 45h F4h MEMORY

13 Register contents before Execution Register contents after Execution
Example LDAX D Instruction: Register contents before Execution 2Bh A 4020h DE Register contents after Execution C2 h A 401F 7Ah 4020 C2h 4021 4022 45h F4h MEMORY 4020h DE 401F 7Ah 4020 C2h 4021 4022 45h F4h MEMORY

14 Register contents before Execution Register contents after Execution
Example STAX B Instruction: Register contents before Execution A4h A 4020h BC Register contents after Execution A4 h A 401F 7Ah 4020 A4h 4021 4022 45h F4h MEMORY 4020h BC 401F 7Ah 4020 C2h 4021 4022 45h F4h MEMORY

15 Register contents before Execution Register contents after Execution
Example LHLD 2005h Instruction: Register contents before Execution 74F1h HL Register contents after Execution 2004 7Ah 2005 C2h 2006 2007 45h F4h MEMORY 45C2h HL 2004 7Ah 2005 C2h 2006 2007 45h F4h MEMORY

16 Register contents before Execution Register contents after Execution
Example SHLD 2005h Instruction: Register contents before Execution 74F1h HL Register contents after Execution 2004 7Ah 2005 F1h 2006 2007 74h F4h MEMORY 74F1h HL 2004 7Ah 2005 A4h 2006 2007 45h F4h MEMORY

17 Register contents before Execution Register contents after Execution
Example LXI B, 1122h Instruction: Register contents before Execution 76DA h BC Register contents after Execution 1122 h BC

18 Register contents before Execution Register contents after Execution
Example XCHG Instruction: Register contents before Execution 1234 h 5678 h HL DE Register contents after Execution 5678 h 1234 h HL DE

19 Arithmetic Instructions
ADD ADD r or M ADC r or M ADI 8 bit data ACI 8 bit data DAD rp (Add register pair to H-L pair) SUB SUB r or M SBB r or M SUI 8 bit data SBI 8 bit data INR r or M DCR r or M INX rp DCX rp DAA

20 Register contents after Execution Register contents before Execution
Example ADD B Instruction: Register contents after Execution 23 h 89 h A B Register contents before Execution 9A h 89 h A B Flag: S=0, Z=0, AC=1 , P=0 and CY=1 Note: All flags are affected during the execution of arithmetic instruction.

21 Register contents after Execution Register contents before Execution
Example ADC B Instruction: Register contents after Execution 24 h 89 h A B Register contents before Execution 9A h 89 h A B Flag: S=0, Z=0, AC=0 , P=0 and C=1 Flag: S=0, Z=0, AC=1 , P=1 and CY=1 1

22 Register contents after Execution Register contents before Execution
Example ADI B2h Instruction: Register contents after Execution 76 h A Register contents before Execution C4 h A Flag: S=0, Z=0, AC=0, P=0 and CY=0 Flag: S=0, Z=0, AC=0 , P=0 and CY=1

23 Register contents after Execution Register contents before Execution
Example ACI 15h Instruction: Register contents after Execution 4E h A Register contents before Execution 38 h A Flag: S=0, Z=0, AC=0 , P=0 and C=1 Flag: S=0, Z=0, AC=0 , P=1 and CY=0 1

24 Register contents before Execution Register contents after Execution
Example DAD B Instruction: Register contents before Execution 2233 h HL 1122 h BC Register contents after Execution 3355 h HL 1122 h BC Note: No flags are affected except Carry Flag.

25 Register contents before Execution Register contents after Execution
Example SUB M Instruction: Register contents before Execution 20 h 8500h A HL Register contents after Execution 18 h A 8500h HL 84FF 7Ah 8500 08h 8501 8502 45h F4h MEMORY 84FF 7Ah 8500 08h 8501 8502 45h F4h MEMORY Flag: S=0, Z=0, AC=0 , P=0 and CY=1 Flag: S=0, Z=0, AC=1 , P=1 and CY=0

26 Register contents after Execution Register contents before instruction
Example SBB B Instruction: Register contents after Execution 1F h 20 h A B Register contents before instruction 40 h 20 h A B Flag: S=0, Z=0, AC=0 , P=0 and C=1 Flag: S=0, Z=0, AC=1, P=0 and CY=0 1

27 Register contents after Execution Register contents before Execution
Example SUI 13h Instruction: Register contents after Execution F2 h A Register contents before Execution 05 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Flag: S=1, Z=0, AC=0, P=0 and CY=1

28 Register contents after Execution Register contents before Execution
Example SBI 13h Instruction: Register contents after Execution 04 h A Register contents before Execution 18 h A Flag: S=0, Z=0, AC=0 , P=0 and C=1 Flag: S=0, Z=0, AC=0, P=0 and CY=0 1

29 Register contents before Execution Register contents after Execution
Example INR E Instruction: Register contents before Execution 1C h E Register contents after Execution 1D h E Note: Except Carry Flag, all flags are affected depend upon the result.

30 Register contents before Execution Register contents after Execution
Example DCR M Instruction: Register contents before Execution 8500h HL Register contents after Execution 8500h HL 84FF 7Ah 8500 07h 8501 8502 45h F4h MEMORY 84FF 7Ah 8500 08h 8501 8502 45h F4h MEMORY Note: Except Carry Flag, all flags are affected depend upon the result.

31 Register contents before Execution Register contents after Execution
Example INX D Instruction: Register contents before Execution A103 h DE Register contents after Execution A104 h DE Note: No Flags are affected.

32 Register contents before Execution Register contents after Execution
Example DCX H Instruction: Register contents before Execution FFFF h HL Register contents after Execution FFFE h HL Note: No Flags are affected.

33 Register contents before Execution Register contents after Execution
Example DAA Instruction: Register contents before Execution 6C h A Register contents after Execution 72 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Flag: S=0, Z=0, AC=1 , P=1 and CY=0

34 Logical Instructions ANA STC (Set Carry) RLC (Rotate accumulator left)
ANA r or M ANI 8 bit data ORA ORA r or M ORI 8 bit data XRA XRA r or M XRI 8 bit data CMA CMC CMP CMP r or M CPI 8 bit data STC (Set Carry) RLC (Rotate accumulator left) RRC (Rotate accumulator right) RAL (Rotate accumulator left through carry) RAR (Rotate accumulator right through carry)

35 Register contents after Execution Register contents before Execution
Example ANA C Instruction: Register contents after Execution 42 h 4A h A C Flag: S=0, Z=0, AC=1 , P=1 and CY=0 Register contents before Execution 62 h 4A h A C Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Note: S, Z, P flags are affected during the execution of AND instruction. CY=0 AC = 1

36 Register contents before Execution Register contents after Execution
Example ANI 15h Instruction: Register contents before Execution 62 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution 00 h A Flag: S=0, Z=1, AC=1 , P=1 and CY=0

37 Register contents after Execution Register contents before Execution
Example ORA C Instruction: Register contents after Execution 6A h 4A h A C Flag: S=0, Z=0, AC=0 , P=1 and CY=0 Register contents before Execution 62 h 4A h A C Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Note: S, Z, P flags are affected during the execution of OR instruction. CY=0 AC = 0

38 Register contents before Execution Register contents after Execution
Example ORI 15h Instruction: Register contents before Execution 62 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution 77 h A Flag: S=0, Z=0, AC=0 , P=1 and CY=0

39 Register contents after Execution Register contents before Execution
Example XRA E Instruction: Register contents after Execution B4 h 5A h A E Flag: S=0, Z=0, AC=0 , P=1 and CY=0 Register contents before Execution EE h 5A h A E Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Note: S, Z, P flags are affected during the execution of XOR instruction. CY=0 AC = 0

40 Register contents before Execution Register contents after Execution
Example XRI 18h Instruction: Register contents before Execution C3 h A Register contents after Execution DB h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Flag: S=0, Z=0, AC=0 , P=1 and CY=0

41 Register contents before Execution Register contents after Execution
Example CMA Instruction: Register contents before Execution 9A h A Register contents after Execution 65 h A Note: No Flags are affected.

42 Register contents before Execution Register contents after Execution
Example RLC Instruction: Register contents before Execution CY A 1 1 1 1 1 1 Register contents after Execution CY A 1

43 Register contents before Execution Register contents after Execution
Example RRC Instruction: Register contents before Execution CY A 1 1 Register contents after Execution CY A 1 1 1

44 Register contents before Execution Register contents after Execution
Example RAL Instruction: Register contents before Execution CY A 1 Register contents after Execution CY A 1 1

45 Register contents before Execution Register contents after Execution
Example RAR Instruction: Register contents before Execution CY A 1 Register contents after Execution CY A 1 1

46 Branching Instructions
Jump Unconditionally Jump Conditionally JC, JNC JP, JM JPE, JPO JZ, JNZ Call Unconditionally Call Conditionally CC, CNC CP, CM CPE, CPO CZ, CNZ Return Unconditionally Return Conditionally RST 46

47 Jump Conditionally Opcode Description Status Flags JC Jump if Carry
CY = 1 JNC Jump if No Carry CY = 0 JP Jump if Positive S = 0 JM Jump if Minus S = 1 JZ Jump if Zero Z = 1 JNZ Jump if No Zero Z = 0 JPE Jump if Parity Even P = 1 JPO Jump if Parity Odd P = 0

48 Call Conditionally Opcode Description Status Flags CC Call if Carry
CY = 1 CNC Call if No Carry CY = 0 CP Call if Positive S = 0 CM Call if Minus S = 1 CZ Call if Zero Z = 1 CNZ Call if No Zero Z = 0 CPE Call if Parity Even P = 1 CPO Call if Parity Odd P = 0

49 Return Conditionally Opcode Description Status Flags RC
Return if Carry CY = 1 RNC Return if No Carry CY = 0 RP Return if Positive S = 0 RM Return if Minus S = 1 RZ Return if Zero Z = 1 RNZ Return if No Zero Z = 0 RPE Return if Parity Even P = 1 RPO Return if Parity Odd P = 0

50 Register contents before Execution Register contents after Execution
Example JMP 8500h Instruction: Register contents before Execution 8000h PC Register contents after Execution 8500 h PC Note: No Flags are affected.

51 Register contents before Execution Register contents after Execution
Example CALL 8500h Instruction: Register contents before Execution 8000h PC 1000 1001 1002 1003 9Ch STACK Register contents after Execution 8500 h PC 1001 h SP SP 00h SP 80h SP Note: No Flags are affected.

52 Branching Instructions
Opcode Operand Description RST 0 – 7 Restart (Software Interrupts) The RST instruction jumps the control to one of eight memory locations depending upon the number. These are used as software instructions in a program to transfer program execution to one of the eight locations. Example: RST 3.

53 Restart Address Table Instructions Restart Address RST 0 0000 H RST 1

54 Control Instructions No operation is performed.
Opcode Operand Description NOP None No operation No operation is performed. The instruction is fetched and decoded but no operation is executed. Example: NOP

55 Control Instructions Opcode Operand Description HLT None Halt The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT

56 Control Instructions Opcode Operand Description DI None Disable interrupt The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected. Example: DI

57 Control Instructions Opcode Operand Description EI None Enable interrupt The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. This instruction is necessary to re-enable the interrupts (except TRAP). Example: EI

58 Control Instructions Opcode Operand Description RIM None Read Interrupt Mask This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. Example: RIM

59 RIM Instruction

60 Control Instructions Opcode Operand Description SIM None Set Interrupt Mask This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM

61 SIM Instruction

62 Example Write a 8085 machine code program for 8 bit addition:
Read two different memory locations Add the contents Send the result to another memory location Store the carry if any, into the next memory location Stop

63 Example 8000 LDA A 8003 MOV B,A 47 8004 LDA A 8007 ADD B 80 8008 JNC XXYY D2 YY XX 8011 MVI C,01 0E 8013 XXYY STA 8016 MOV A,C 79 8017 STA 801A HLT 76 Load contents of memory location 8500 into accumulator Save the first number in B Load contents of memory location 8501 into accumulator Add accumulator with B Jump to YYXX if no carry ! Store the carry in C register Send the result to 8052 Copy the Carry to A register Store the Carry into 8503 Stop

64 Updated Code 8000 LDA 8500 3A 8001 00 8002 85 8003 MOV B,A 47
8003 MOV B,A 47 8004 LDA A 8007 ADD B 80 8008 JNC 800D D2 D 800A 800B MVI C,01 0E 800C 800D XXYY STA 800E 800F 8010 MOV A,C 79 8011 STA 8014 HLT 76 Load contents of memory location 8500 into accumulator Save the first number in B Load contents of memory location 8501 into accumulator Add accumulator with B Jump to YYXX if no carry ! Store the carry in C register Send the result to 8052 Copy the Carry to A register Store the Carry into 8503 Stop 64

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