How to use ISE Dept. of Info & Comm. Eng. Prof. Jongbok Lee

A. Introduction Xilinx ISE (Integrated Software Environment) –VHDL/Verilog coding –Synthesis –FPGA Programming & Implementation

I. Start Double click Xilinx ISE 10.1i –Project Navigator appears File  New Project New Project window –Project Name : proj_name –Top-Level Module Type : HDL –Click [next] –File ***.ise is created

New Project window –Device Family : Spartan3 –Device : xc3s400 –Package : FT256 –Speed Grade : -4 –[next][next][finish]

II. VHDL Coding Project  New Source –Select VHDL Module –File Name : myinv Project  Add Source –You can add an existing vhdl source Define VHDL Source window –Port Name : Direction –a: in –b: out –[next][finish]

–if VHDL window appears, File  Save Source window : Source for Synthesis/Implementation –You can double click Check Syntax and find the syntax error Architecture Behavioral of myinv is begin b <= not(a); end Behavioral

IV. Synthesis Source window : select Synthesis/Implementation –Synthesize-XST click Check Syntax if wrong, see the View Synthesis Report and fix it. if right Save FPGA pin number assigment –Source window: select myinv.vhd –Process window: User Constraints  Floor Plan IO - Pre Synthesis Xilinx PACE window appears Design Object List-I/O Pins –I/O Name : I/O Direction : Loc –a : Input :G3 –b : Output :A12 File  Save

Note –In one project, only one module can be synthesized. –if the User Constraint, Synthesize- XST,Implement, Generate menu does not appear in the process window, select module, click right mouse button and select to execute Set As Top Module –Then the three triangle appears in front of the module.

Implementation –Translate : transform the netlist into the inner format –Map : optimize and then map the logic circuits to the FPGA resources such as CLB and IOB. –Place & Route : connect the gates allocated in CLBs

note –CLB(Configurable Logic Block) consists of 3 LUTs(Look Up Table) and 2 Flip Flops the basic block that constitutes FPGA

Synthesize and P&R –Process window : double click Synthesize- XST –Process window : double click Implement Design

EDA-Lab II Experiment Kit Function : An equipment for the verification of FPGA circuit design Usage : education, circuit development FPGA capacity : 400,000 gates Supporting software : Design Pro Shop

V. Emulation Emulation ? –a hardware mimics another hardware How to set up –connect EDA-Lab 2’s Xilinx USB JTAG port to PC. –connect main board’s Jumper pin and targer FPGA’s Expansion Port by cable (JP6.0~CN1.17). –Turn on the Power. –The cable colors should be matched in correspondence.

Generating an FPGA programming file –Process window : Double click Generate Programming File See the Programming File Generation Report –make sure myinv.bit has been created. –It should be in the project folder.

iMPACT Process window –Configure Target Device Manage Configuration Project(iMPACT) –File  Initialize Chain –Assign New Configuration File : myinv.bit [open] –[bypass] –select xc3s400 and click the right mouse button  program : Program Succeeded !

[2] Full Adder Data Flow Modeling entity full_adder is port (a,b,ci : in std_logic; sum, co : out std_logic); end full_adder; architecture Behavioral of full_adder is begin co <= (a and b) or (b and ci) or (ci and a); sum <= a xor b xor ci; end Behavioral; a : G3 b: G4 ci: H3 sum : A12, JP6.0~CN1.17 co : A14, JP6.1~CN1.18

Inputs Push Button –G3,G4,H3,H4 DIP Switch –R16,C16,B16,G14,G15,L13,M14,G1

DPS(Design Pro Shop) –usage : emulation software –function : designate FPGA, generate test patterns –install : In CD’s SetUp folder, run SetUp.exe –run portnt95.exe –while rebooting the PC, press F2, CMOS SetUp, peripheral, EPP mode, save

How to emulate with DPS –Double click DPS 3.1 –select Tool  Download –push Browse and select myinv.bit –Successfully Downloaded message appears. –View  Single Step Mode, input signals and click Write –View  Waveform Mode, you can see the waves

View  Multi Step Mode –Edit  Add : lines appear(or click ‘+’ symbol). –Input 16 digits either in Binary or Hexa. ex) or 0008 (which is simpler?) –Edit  Select All (or Ctrl-C). –Port  Run (or symbol ’  ’):automatically processes and outputs generated in binary and hexa. Tool  Option  Timing –Interval For Running 500ms may be changed.

Multi Step Mode

Multi Step Mode I/O Hexa-decimal input and hexa-decimal output is recommended Without input, rest of the digits are filled with zero automatically. When not connected by cable, the hexa- decimal digit is F’s(1111) –ex1) 16 = ( ), hence F0. –ex2) 9 = ( ) hence F9.

DPS Emulation Result FFFC FFFD FFFD FFFE FFFD FFFE FFFE FFFF