1. Chapter 5. Code converter
Dept. of Info. & Comm. Eng.
Prof. Jongbok Lee

2. Code converter
Usage : When exchanging information among systems which have different code systems, must convert codes
Types
BCD code
Excess-3 code
Gray code

3. 1. BCD Code Alias : Binary Coded Decimal, 8421 code
Meaning : represent each decimal to four-digit
Feature : weighted code(can be used for calculation)
Example :
0~9 same as binaries
10 :
11 :

4. Decimal
Binary
BCD
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
1010 11
1011

5. 2. Excess-3 code Meaning : add 3 to BCD code Feature :
Self-complement code
Non-weighted code

6. Decimal
Excess-3
0011 1
0100 2
0101 3
0110 4
0111 5
1000 6
1001 7
1010 8
1011 9
1100 10 11

7. entity bcd2excess3 is
port ( bcd : in std_logic_vector(3 downto 0);
excess3 : out std_logic_vector(3 downto 0));
end bcd2excess3;
architecture behavioral of bcd2excess3 is
begin
excess3 <= “0011” when (bcd=“0000”) else
“0100” when (bcd=“0001”) else
“0101” when (bcd=“0010”) else
“0110” when (bcd=“0011”) else
“0111” when (bcd=“0100”) else
“1000” when (bcd=“0101”) else
“1001” when (bcd=“0110”) else
“1010” when (bcd=“0111”) else
“1011” when (bcd=“1000”) else
“1100”;
end behavioral;

8. entity bcd2excess3 is
port ( bcd : in std_logic_vector(3 downto 0);
excess3 : out std_logic_vector(3 downto 0));
end bcd2excess3;
architecture behavioral of bcd2excess3 is
begin
process(bcd)
case (bcd) is
when “0000” => excess3 <= “0011”;
when “0001” => excess3 <= “0100”;
when “0010” => excess3 <= “0101” ;
when “0011” => excess3 <= “0110” ;
when “0100” => excess3 <= “0111” ;
when “0101” => excess3 <= “1000” ;
when “0110” => excess3 <= “1001” ;
when “0111” => excess3 <= “1010” ;
when “1000” => excess3 <= “1011”;
when others => excess3 <= “1100”;
end case;
end process;
end behavioral;
% 실험
손을 떼면 1111 입력 : LED on-on-off-off 출력 1100
모두 누르면 0000입력 : LED off-off-on-on 출력 0011
양쪽 끝을 누르면 0110 입력 : LED on-off-off-on 출력 1001

9. #PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "bcd<0>" LOC = "H4" ;
NET "bcd<1>" LOC = "H3" ;
NET "bcd<2>" LOC = "G4" ;
NET "bcd<3>" LOC = "G3" ;
NET "excess3<0>" LOC = "A12" ;
NET "excess3<1>" LOC = "A14" ;
NET "excess3<2>" LOC = "B14" ;
NET "excess3<3>" LOC = "B13" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
P16 D9 C9
C12
B13
B14
A14
A12 G3 G4 H3 H4

10. signal pin (push) pin (DPS) cable connection bcd(0) JP4.0 CN3.22
excess(0)
A12
JP6.0
CN1.17
excess(1)
A14
JP6.1
CN1.18
excess(2)
B14
JP6.2
CN1.19
excess(3)
B13
JP6.3
CN1.20

11. 3. Gray Code
Meaning : For the adjacent digits, only 1 bit is different
Feature
Non-weighted code (cannot be used for calculation)
minimum chage code

12. Decimal
Gray
0 (0000)
0000
1 (0001)
0001
2 (0010)
0011
3 (0011)
0010
4 (0100)
0110
5 (0101)
0111
6 (0110)
0101
7 (0111)
0100
8 (1000)
1100
9 (1001)
1101
10 (1010)
1111
11 (1011)
1110
% 실험
(1) 모두 누르면 off-off-off-off
(2) 누르고-누르고-누르고-떼면 off-off-off-on
(3) 누르고-떼고-떼고-누르면
off-on-off-on

13. entity bin2gray is
port (binary : in std_logic_vector(3 downto 0);
gray : out std_logic_vector(3 downto 0));
end bin2gray;
architecture behavioral of bin2gray is
begin
gray(3) <= binary(3);
gray(2) <= binary(2) xor binary(3);
gray(1) <= binary(1) xor binary(2);
gray(0) <= binary(0) xor binary(1);
end behavioral;

14. signal pin (push) pin (DPS) cable connection binary(0) JP4.0 CN3.22
gray(0)
A12
JP6.0
CN1.17
gray(1)
A14
JP6.1
CN1.18
gray(2)
B14
JP6.2
CN1.19
gray(3)
B13
JP6.3
CN1.20

15. entity gray2bin is
port ( gray : in std_logic_vector(3 downto 0);
binary : out std_logic_vector(3 downto 0));
end gray2bin;
architecture Behavioral of gray2bin is
signal tmp : std_logic_vector(3 downto 0);
begin
tmp(3) <= gray(3);
tmp(2) <= gray(2) xor tmp(3);
tmp(1) <= gray(1) xor tmp(2);
tmp(0) <= gray(0) xor tmp(1);
binary <= tmp;
end Behavioral;

16. signal pin (push) pin (DPS) cable connection gray(0) JP4.0 CN3.22
binary(0)
A12
JP6.0
CN1.17
binary(1)
A14
JP6.1
CN1.18
binary(2)
B14
JP6.2
CN1.19
binary(3)
B13
JP6.3
CN1.20

17. entity pin_test is
port ( input : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0));
end pin_test;
architecture behavioral of pin_test is
begin
led <= input;
end test;

18. signal pin no. cable connection input(0) D7 JP4.0 CN3.22 input(1) C7
led(0)
A12
JP6.0
CN1.17
led(1)
A14
JP6.1
CN1.18
led(2)
B14
JP6.2
CN1.19
led(3)
B13
JP6.3
CN1.20
led(4)
C12
JP6.4
CN1.21
led(5) C9
JP6.5
CN1.22
led(6) D9
JP6.6
CN1.23
led(7)
P16
JP6.7
CN1.24

19. % The emulation hexa inputs for Design Pro Shop00 55 AA 01 02 04 08 10 20 40 80