EE 345S Real-Time Digital Signal Processing Lab Fall 2008 Lab #3 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6713 DSP (Continued) Wael Barakat

2 Outline Outputting Using Direct Memory Access (DMA) Sine Wave Generation Using Difference Equation

3 DMA In polling and interrupts methods, usage of sin(.) function repeatedly consumes CPU cycles, which is computationally inefficient. Solution: Use EDMA capabilities of the C6713 to read samples from a pre-computed table and load them into a McBSP DXR for transmission to a codec.

4 EDMA Idea is that, with EDMA, CPU can initiate data transfer and do other operations while transfer is in progress. More efficient than using regular I/O which keeps CPU occupied during entire transfer. EDMA controller:  Handles all data transfers between L2 cache and peripherals.  Can move data to and from any addressable memory spaces (internal memory, external memory and peripherals) independently of CPU operations.

5 EDMA Features Has 16 channels that can be assigned priorities. Data transfers can be initiated by CPU or events. Transfers can be 8-bit bytes, 16-bit half-words, or 32-bit words. Can transfer 2-dimensional data blocks. When an event occurs its transfer parameters are read from the Parameters RAM (PaRAM) and then sent to the address generation hardware.

6 EDMA Features After an element transfer, addresses at source/destination can stay the same, get incremented or decremented. After a programmed transfer, EDMA can continue transfers by linking to another transfer programmed in the PaRAM for same channel, or chaining to a transfer for another channel Can generate transfer completion interrupts to the CPU along with a transfer complete code, for it to take desired action based on that code. EDMA has a Quick DMA mode (QDMA) for quick, one- time transfers.

7 DMA Each of the 16 channels has a default event (on peripheral devices) associated with it which triggers the data transfer. User can change mapping by modifying EDMA Event Select registers ESEL0, ESEL1 and ESEL3.

8 DMA Event Processing Registers:  Event Register (ER): when event n occurs, bit n of ER is set.  Event Enable Register (EER): setting bit n of EER enables processing of that event.  Event Clear Register (ECR): setting a bit in ECR clears corresponding bit in ER, used by CPU to clear event flags.  Event Set Register (ESR): setting a bit in ESR sets corresponding bit in ER, used by CPU to submit event requests and for debugging.

9 DMA Parameter RAM (PaRAM):  Transfer parameter table for EDMA channels is stored in PaRAM.  It is a 2KB block of RAM located within EDMA.  Table consists of 24 bytes that contain all information about a transfer.

10 DMA The OPT field:  Sets the priority,  Sets the element size: 8, 16, or 32 bits,  Defines sources as 1- or 2-dimensional,  Enables/disables transfer complete interrupt,  Defines transfer complete code,  Sets source/destination address update modes.

11 DMA A 1-D block transfer consists of FRMCNT+1 frames. Each frame consists of ELECNT elements. Type 1 Transfer, if FS=0 in OPT field (sync event occurs, for example transition of McBSP XRDY flag from FALSE to TRUE for example)  A frame element is transferred from source to destination.  S/D Addresses are updated in parameter set after transfer.  ELECNT decremented by 1.

12 DMA When ELECNT reaches 1, i.e. final element in frame,  Element is transferred,  ELECNT is reloaded with value in ELERLD.  FRMCNT is decremented by 1. EDMA continues to transfer data at sync events until no more frames are available. Type 2 Transfer, if FS=1 in OPT field, each sync event causes all elements of a frame to be transferred as rapidly as possible.

13 DMA Linking EDMA Transfers:  When LINK bit of OPT is 0, EDMA stops after a transfer is complete.  If LINK=1 and transfer is completed, Transfer parameters are reloaded with parameter set pointed to by 16-bit address located in LINK field. EDMA continues with transfer of new set.

14 DMA EDMA Interrupts to CPU  If Transfer Complete Interrupt (TCINT) bit is set to 1 in OPT field for a channel and event mapped to that channel occurs, EDMA will set a bit in Channel Interrupt Pending Register (CIPR).  Then, if bit corresponding to channel in Channel Interrupt Enable Register (CIER) is set, EDMA generates EDMA_INT interrupt to CPU.  If EDMA_INT is enabled in IER, program execution will jump to ISR.

15 Sine Wave Generation Difference Equation:  Input x[n] is an impulse.  Output y[n] are cosine/sine values.  IC’s are all zero.  Computation: 2 multiplications and 3 or 2 additions  Memory Usage: 2 coefficients, 2 previous values of y[n] and 1 previous value of x[n]  Drawback is the build-up of error due to feedback sin(  0 n).u[n] ↔ y[n] = 2.cos(  0 ).y[n-1] - y[n-2] - sin(  0 ).x[n-1]