1. MPC8360 Micro Controllers 371-1-2403
Lab 7 - DMA
Fall , 2010

2. Direct Memory Access (DMA)
Let’s Copy 1 MB from A to B
E300 Core
Memory Controller
Core busy Reading & Writing
External Memory

3. Direct Memory Access (DMA)
Let’s Copy 1 MB from A to B
E300 Core
Memory Controller
DMA
0x8000
Core Is Free
External Memory

4. DMA Source Address Register (DMASAR0)
Offset 0x110 31
R W SA
Reset
All Zeros
Warning
Registers described in this section use Little-Endian byte ordering

5. DMA Source Address Register (DMASAR0)
Offset 0x110 31
R W
Reset
All Zeros SA SA
Source Address
Source address of DMA transfer. The content of this field is updated after each DMA read operation.

6. 1 2 3 4 A B C D Little Endian Example 0x 1 2 3 4 _ A B C D
Offset 0x110 31 24 23 16 15 8 7
R W
Reset
All Zeros
1 2
3 4
A B
C D
0x _ A B C D
Source Address
R3 =
0x C D A B _
DMASAR0 = R3

7. DMA Destination Address Register (DMADAR0)
Offset 0x118 31
R W
Reset
All Zeros

8. DMA Destination Address Register (DMADAR0)
Offset 0x118 31
R W
Reset
All Zeros DA DA
Destination Address
Destination address of DMA transfer. Updated after each DMA write operation.

9. DMA Byte Count Register (DMABCR0)
Offset 0x120 31 26 25
R W
____ BC
Reset
All Zeros

10. DMA Byte Count Register (DMABCR0)
Offset 0x120 31 26 25
R W
____ BC
Reset
All Zeros BC
Byte Count
This field contains the number of bytes to transfer. The value in this register is decremented after each DMA read operation. Maximum transfer size is 64 Mbytes.

11. DMA Mode Register (DMAMR0)
Offset 0x100 31 7 2 1
R W …
EOTIE
CTM CS
Reset
All Zeros

12. DMA Mode Register (DMAMR0)
Offset 0x100 31 7 2 1
R W …
EOTIE
CTM CS
Reset
All Zeros
EOTIE
End-of-transfer Interrupt Enable This bit determines whether an interrupt is generated at the completion of a DMA transfer.
No EOT interrupt is generated 1
EOT interrupt is generated

13. DMA Mode Register (DMAMR0)
Offset 0x100 31 7 2 1
R W …
EOTIE
CTM CS
Reset
All Zeros
CTM
Channel Transfer Mode
Chaining mode 1
Direct mode

14. DMA Mode Register (DMAMR0)
Offset 0x100 31 7 2 1
R W …
EOTIE
CTM CS
Reset
All Zeros CS
Channel Start
A 0-to-1 transition occurring on this bit when the channel is not busy (SR[CB] bit is 0) will
start the DMA process.

15. DMA Status Register (DMASR0)
Offset 0x104 31 2
R W … CB
EOCDI
Reset
All Zeros

16. DMA Status Register (DMASR0)
Offset 0x104 31 2
R W … CB
EOCDI
Reset
All Zeros CB
Channel Busy. This bit indicates whether the channel is busy. It is cleared as a result of any of the following conditions: (1) an error, (2) a halt, or (3) completion of the DMA transfer.
No DMA transfer is currently in progress 1
A DMA transfer is currently in progress

17. DMA Status Register (DMASR0)
Offset 0x104 31 2
R W … CB
EOCDI
Reset
All Zeros
EOCDI
End-Of-Chain/Direct Interrupt.
When the last DMA transfer is finished, either in chaining or direct mode, if DMAMR[EOTIE] is set, this bit is set and an interrupt is generated.

18. System Internal Interrupt Mask Register (SIMSR_L)
E300 Core
DMA
Interrupt Controller
DMA
The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

19. System Internal Interrupt Mask Register (SIMSR_L)
E300 Core
Offset 0x724 7 31
DMA
DMA
Interrupt Controller
DMA
The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

20. Machine State Register (MSR)
E300 Core
DMA
Interrupt Controller
DMA
The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

21. Machine State Register (MSR)
E300 Core …. 16
….. 31 EE
DMA
Interrupt Controller
DMA
The user can mask an interrupt by clearing (setting the bit to 0) the relevant bit.

22. RAID - Redundant Array of Independent Disks
A technology that provides: increased storage reliability and/or increased input/output performance through the usage of multiple relatively low-cost, less-reliable disk drives.
The various types of RAID types or architectures are named by the word RAID followed by a number (e.g., RAID 0, RAID 1)

23. RAID 0 (block-level striping)
Data is written in stripes to multiple disks (striping).
Storage Reliability ?
No increased storage reliability, in fact any disk failure destroys the array, and the likelihood of failure increases with more disks in the array
Performance ?
Improved performance since data can be read and written in parallel. A4 A3 A2 A3 A4 A1 A1 A2
File
Disk 0
Disk 1

24. RAID 1 (mirroring)
Data is written identically to multiple disks (a "mirrored set").
Storage Reliability ?
Provides fault tolerance from disk errors or failures and continues to operate as long as at least one drive in the mirrored set is functioning.
Performance ?
Increased read performance, and only a minimal write performance reduction. A4 A1 A2 A3 A4 A1 A2 A3 A4 A3 A2 A1
File
Disk 0
Disk 1

25. RAID 4 (block-level striping with parity)
Distributes parity along with the data. A4 A3 A2 A3 A4
Parity A1 A1 A2
Parity
File
Disk 0
Disk 1
Disk 2

26. RAID 4 - Example 0b 0b 0b
Disk 0
Disk 1
Disk 2

27. RAID 4 - Example 0b 0b 0b
Disk 0
Disk 1
Disk 2

28. RAID 4 (block-level striping with parity)
Storage Reliability ?
The array is not destroyed by a single drive failure. Upon drive failure, any subsequent reads can be calculated from the distributed parity.
Performance ?
Increased read performance, but substantial write performance reduction. A4 A3 A2 A3 A4
Parity A1 A1 A2
Parity
File
Disk 0
Disk 1
Disk 2

29. Loading a File to the Memory
In Debug Mode

30. General Notes
Make sure to bring the codes you have written in previous labs.
Please READ the exercise before you start working on it !!

31. Quick Overview