IEEE 1394b Real-Time Systems Lab. 박 준 호

Real Time Systems Lab. Contents IEEE 1394 Overview IEEE 1394 Specifications P1394a, P1394b, P1394.1, OHCI IEEE 1394 Architecture Transfers and transactions Arbitration 1394b

Real Time Systems Lab. IEEE 1394 Overview Serial bus Architecture ISO/IEC CSR(Control Status Register) Architecture Key Features Scalable Performance: 100, 200 and 400 Mb/s Hot Insertion & Removal, Plug and Play Support for two types of transactions: Asynchronous and Isochronous Support for 64 nodes Address space of 16petabytes per bus Support for 1024 buses Peer-to-Peer transfer support Cable power

Real Time Systems Lab. IEEE 1394 Specifications Specification and Related Document IEEE 1394a Supplement Power Distribution Specification Power Management Specification Suspend/Resume Specification Open Host Controller Interface (OHCI) for 1394 Specification Device Bay Specification Bridge Specification IEEE 1394.B Specification

Real Time Systems Lab. IEEE 1394a Basic improvements, “P1394a” The improvements include: Arbitration accelerations Reset improvements Support for fine-grained power management

Real Time Systems Lab. IEEE 1394b New technology, “P1394b” The existing P1394b draft specifies: Speeds up to 1.6 Gbit/sec ~ 3.2 Gbit/sec Node-to-node distances to over 100m using various media Cost reductions over the existing and p1394a implementations

Real Time Systems Lab. IEEE & OpenHCI Networks, “P ” connections between multiple 1394 busses Basic model: two portal bridge OHCI 1394 single programming model to access all link-layer implementations

Real Time Systems Lab. IEEE 1394 Architecture ISO/IEC Node architectures Address space Common transaction types Control and Status Registers (CSRs) Configuration ROM format and Content Message broadcast mechanism to all nodes or to units within a node Interrupt broadcast to all nodes

Real Time Systems Lab. Node Architecture Module, Node, Unit

Real Time Systems Lab. Address Space 64bit address space – bus(0:9), node(10:15), memory(16:63)

Real Time Systems Lab. Transfers and Transactions Cycle – 125usec Asynchronous Transfers (20%) Read, Write, Lock Request transactions: address, command, and data Response transactions: status Locked transaction: read-modify-write operations, atomic operation Isochronous Transfers (80%) Constant rate, not require confirmation of data delivery Isochronous talker, listener

Real Time Systems Lab. Arbitration Guaranteed bus bandwidth for isochronous channels and a fairness interval for asynchronous channels Cycle time: 125 us Fair, Priority, Immediate, Isochronous arbitration

Real Time Systems Lab. 1394a Arbitration Enhancements Reduce subaction gap delay Acknowledge accelerated arbitration Fly-by arbitration

Real Time Systems Lab. IEEE 1394b Introduction Purpose Working Group BOSS arbitration PIL-FOP Zayante Presentation

Real Time Systems Lab. Introduction In the winter of 1997 at a meeting of the 1394TA Problem of 1394 It is not DC balanced made it impractical to use over longer distance Accumulated skew on a long distance connection make it hard to maintain the timing relationships between the data and strobe lines New signaling scheme (Beta mode) 8b-10b coding, bi-lingual ports Expanded the scope of the work Divide the P1394B working group into various task groups

Real Time Systems Lab. 1394b Purpose Technology advances have made gigabit signaling a feasible and attractive extension to the baseline 1394 standard Higher speed and longer distance interconnect bus than can be provided by the IEEE std and IEEE 1394a-2000

Real Time Systems Lab. 1394b working group Glass Fiber, Plastic Fiber, UTP5 Standard Electrical the electrical characteristics for the base-line PHY Start-up protocol the speed signal scheme using a toning mechanisms, loop- breaking protocol Cable & Connector characterize the 4 and 6 circuit connectors for use at the higher speeds defined in this standard.

Real Time Systems Lab. 1394b working group Protocol Accelerations Arbitration scheme Port Logic Developed the coding and scrambling methods used for Bata mode ports Simulation Low-Power PHY-link/PIL-FOP C-Code

Real Time Systems Lab. Overview High Speeds to 3.2 Gbit/sec New coding (8b10b) New Arbitration (BOSS) Overlapped, pipelined arbitration, hybrid bus operation for backward compability Long distance to 100m per hop New media, but all compatible the media dependent level New Integration Model (PIL-FOP)

Real Time Systems Lab. BOSS Arbitration BOSS (Bus Owner/Supervisor/Selector) Determine the end of the fairness interval and the end of isochronous intervals Select the path to grant next BOSS Arbitration Arbitration request signaling is overlapped with data transmission on the full-duplex bus Both isochronous and asynchronous requests may be pipelined for servicing in the succeeding isochronous interval and fairness interval, respectively Tokens: CYCLE_START_EVEN/ODD, ASYNCH_START, ARBRST_EVEN/ODD

Real Time Systems Lab. PIL-FOP Interface between a link and a discrete PHY for all Serial Bus speeds (S100, S200, S400, S800 and S1600) PIL: a PHY with a single Beta port is integrated into a link FOP: Beta capable port on a fan-out PHY Operation model: PIL effectively serves the role of a traditional link, while the FOP operates as the effective PHY in the system.

Real Time Systems Lab. PIL-FOP PC chipset vendor integrates PIL into chipset PC OEM chooses FOP based on market requirements

Real Time Systems Lab. TI 1394b product Real-time data transfer for multimedia applications 100, 200, & 400Mbits/s data rates today; 800 Mbits/s and multi- Gbits/s upgrade path Free form network tool allowing mixing branches and daisy-chains Guaranteed bandwidth assignments for real-time applications Compliant with IEEE and 1394a High Performance Serial Bus standard

Real Time Systems Lab.