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Kristian Naess Qicai Guo Roy Torres Mark Bacchus Yue Kun Alberto Chestaro.

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Presentation on theme: "Kristian Naess Qicai Guo Roy Torres Mark Bacchus Yue Kun Alberto Chestaro."— Presentation transcript:

1 Kristian Naess Qicai Guo Roy Torres Mark Bacchus Yue Kun Alberto Chestaro

2  The three key elements to a computer are: Processor(CPU), memory, and I/O devices  I/O devices are called peripherals. Peripherals can be classified as: Human Readable, Machine Readable, and Communication.  Input devices. Examples: mouse, keyboard, joystick, scanners, microphone, ect.  Output devices. Examples: monitors, speakers, printer, ect.

3  Peripherals are connected through I/O modules.  Data transfers significantly slower than memory and processor.

4  Basic and major function of a module: Control and Timing Processor Communication Device Communication Data Buffering Error Detection

5  Three type of signals: Control Signal Data Signal Status Signal

6  Basic and major function of a module: Control and Timing Processor Communication Device Communication Data Buffering Error Detection


8  Three types of I/O operations: Interrupt Non-Interrupt Programmed



11  What is the problem with programmed I/O ? Delays  Any solutions to this problem ? Issue an I/O command  do some useful work

12  Why are interrupts useful ? External analogy to exceptions Allow response to unusual external events without inline overhead (polling)  Idea: Use interrupts to reduce polling overhear for Input/output Processor initiates I/O operations Device interrupts processor when its ready Interrupt handler transfers data into memory Control returned to currently executing program

13 Device controller or other system hardware issue an interrupt Processor finishes execution of current instruction Processor signals acknowledgment of interrupt Processor pushes PSW and PC onto control stack Processor loads new PC value based on interrupt Save remainder of process state information Process interrupt Restore process state information Restore old PSW and PC

14  How does the processor determines which device issued the interrupt ?

15 The most straightforward approach Impractical to use Multiple I/O modules attached Multiple interrupt lines Time Consuming Poll each I/O module to determine which module caused the interrupt Software Poll More efficient It provides a hardware poll Daisy Chain Must gain control of the bus before it can raise the interrupt requested line In responds on the interrupt acknowledge line Bus arbitration

16 Advantages  Reduced vs. interrupt cost polling time  Improved program modularity (no more polling code)  Preserves the ability of old programs to run in new configurations Complications  Additional hardware required (interrupt controller, etc)  How to deal with several devices ?  What if more than one interrupt occurs at one ?

17  Processor sets up I/O operation, continues its work  Device performs I/O (a long time)  Device completes, interrupts the processor  Processor responds to interrupt, transfers the data  I/O is complete.  => Interrupts save overhead of polling. PMem I/O Memory Bus I/O Bus











28 There are two major characteristics of interface: Parallel Interface- which involves multiple lines to transfer data Serial Interface- which only has one line to transmit data

29 Parallel Multiple bits are transferred simultaneously, just as all of the bits of a word are transferred simultaneously over the data bus Traditionally been used for higher-speed peripherals Serial Bits must be transmitted one at a time Traditionally been used for printers and terminals new generation of high- speed serial interfaces, are making parallel interfaces much less common.


31 Point-to-Point interface provides a dedicated line between the I/O module and the external device. Multipoint interfaces are in effect external buses and they exhibit the same type of logic as the buses

32 There has been great interest in developing a high-speed alternative to Small Computer System Interface (SCSI) and other small-system I/O interfaces. The result is the IEEE standard 1394,for a High Performance Serial Bus, commonly known as FireWire. It is very high speed, low cost, and easy to implement. One of the strengths of the FireWire interface is that it uses serial transmission (bit at a time) rather than parallel.

33 Uses a daisy-chain configuration (Tree-structure) up to 63 devices connected off a single port up to 1022 FireWire buses can be interconnected using bridges, enabling a system to support as many peripherals as required. Provides hot plugging Provides Automatic configuration



36 The three layers (Stacks)  Physical Layer- Defines the transmission media that are permissible under FireWire and the electrical and signaling characteristics of each  Link Layer-Describes the transmission of data in the packets  Transaction Layer-Defines a request–response protocol that hides the lower-layer details of FireWire from applications

37 Physical specifies several alternative transmission media and their connectors, with different physical and data transmission properties converts binary data into electrical signals for various physical media provides the arbitration service that guarantees that only one device at a time will transmit data Contains logic that allows all the attached devices to configure themselves so that one node is designated as the root of the tree and other nodes are organized in a parent/child relationship forming the tree topology

38 Link Two types of transmission are supported: Asynchronous: A variable amount of data and several bytes of transaction layer information are transferred as a packet to an explicit address and an acknowledgment is returned. Isochronous: A variable amount of data is transferred in a sequence of fixed-size packets transmitted at regular intervals

39 Is a recent I/O specification aimed at the high-end server market Not necessary to have the basic I/O interface hardware inside the server chassis net- working, and connections between servers are accomplished by attaching all devices to a central fabric of switches and links Unlike PCI, InfiniBand’s channel design enables I/O devices to be placed up to 17 meters away from the server using copper, up to 300m using multimode optical fiber, and up to 10 km with single-mode optical fiber

40  InfiniBand uses virtual lanes

41 Physical: Specification defines three link speeds (1X,4X, and 12X) giving transmission rates of 2.5, 10, and 30Gbps, respectively. The physical layer also defines the physical media, including copper and optical fiber. Link: Defines the basic packet structure used to exchange data, including an addressing scheme that assigns a unique link address to every device in a subnet. It also, includes the logic for setting up virtual lanes and for switching data through switches from source to destination within a subnet. Network: Routes packets between different InfiniBand subnets. Transport: Provides reliability mechanism for end-to-end transfer of packets across one or more subnets.


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