The SuperB EMC Front End electronics Prototypes Valerio Bocci 2009 INFN sezione di Roma Valerio Bocci A. Papi, C. Cecchi, P. Lubrano (INFN Perugia) M. Capodiferro, G. Chiodi, R.Faccini, L. Recchia,D. Ruggieri (INFN Roma)

SuperB EMC structure SuperB EMC Barrel = BaBar EMC Barrel 5760 CsI(Tl) Crystals SuperB EMC Forward = 3600 Lyso Crystals or 360 CsI(TI) BaBar Ring Lyso BaBar Crystals are radiation damaged. Need replacement Valerio Bocci 2009

480 ADB /6 = 80 IOB ADB IOB 12 x CsI(TI) preamp Crates (80) (80) 5760 preamp /12= 480 ADB Optical Link The EMC Front End Electronics SuperB=Babar Need new design Valerio Bocci 2009

ECS in the overall system

Prototypes boards goal Test components and architectures Create a simple system to play whith different parameters Valerio Bocci 2009

Prototypes boards VFE Front End interface Digitizer Board FPGA data aggregator and PC readout for testing purpose VFE Digitizer Board Xilinx Opal Kelly USB 2.0 Ctrl Lines Valerio Bocci 2009 PIN/APD

The EMC Forward read out options 2 x APD (5x5mm) 2 x PIN (10x10mm) 1 x PIN ( 20x10mm ) CSP + shaper (Number CsI(TI) Forward endcap babar *4) Number of Lyso crystals =3600 TIA or TA We start to test Charge sensitive preamp at Beam Test Facility in Frascati Valerio Bocci 2009

APD or PIN readout X 50 X V/pC X V/pC (APD amplification x 10) Pin Solution 10x20 mm Area=apd x 4 M=1 APD Solution Valerio Bocci 2009

Energy Scan (From Alessandro Rossi EMC presentation) Valerio Bocci 2009

Prototypes boards VFE Front End interface Digitizer Board FPGA data aggregator and PC readout for testing purpose VFE Digitizer Board Xilinx Opal Kelly USB 2.0 Ctrl Lines Valerio Bocci 2009 PIN/APD

CSP (CR110, OPAMPCSP) Differential Line Driver (AD8131) PIN PD Very Front End Board VFE 2 Valerio Bocci V/pC mV/Mev 13 Gev 1048 mV 200MeV 16 mv AD8131 x16 OPA657 AD8130 / 29 LED PIN /APD Adapter connector 1/ mV

Old ADB Energy resolution Valerio Bocci 2009

12 bits single ADC resolution It is impossible to cover all the dynamic with a good resolution BAD

Energy Resolution using 2 Ranges MeV % ADC0 LSB/ Mev % ADC1 LSB/ Mev % ADC selected/ MeV OVF OVF OVF0.02 Valerio Bocci 2009

Prototypes boards VFE Front End interface Digitizer Board FPGA data aggregator and PC readout for testing purpose VFE Digitizer Board Xilinx Opal Kelly USB 2.0 Ctrl Lines Valerio Bocci 2009 PIN/APD

Differential Receiver (8130) Programmable Gain Amplifier (AD8369) 2 12Bits ADC 12bits ADC (ADS6422) 1/4 Differential Receiver(8130) Mev 200 MeV–13 Gev Latch serializer Valerio Bocci 2009 Digitizer Board Prototype DAC X4 Range Bit Transmitter f/6 56 MHz FTCS interf 9.3 MHz Fsx6 (DDR) ECS (ctrl interface) Shaper (CR ) x10 SN65LV1023A Shaper (CR ) Cal range TLV3502 Adj Fine Gain RST x10

Differential Receiver (8130) Programmable Gain Amplifier (AD8369) 2 12Bits ADC 12bits ADC (ADS6422) 1/4 Differential Receiver(8130) Mev 200 MeV–13 Gev Latch serializer Valerio Bocci 2009 Calibration settings DAC X4 Range Bit Transmitter f/6 56 MHz FTCS interf 9.3 MHz Fsx6 (DDR) ECS (ctrl interface) Shaper (CR ) Shaper (CR ) x10 SN65LV1023A Shaper (CR ) Cal range=0 TLV3502 Adj Fine Gain RST MHz

Resolution in case of Calibration Settings 6 MeV resolution

Prototypes boards VFE Front End interface Digitizer Board FPGA data aggregator and PC readout for testing purpose VFE Digitizer Board Xilinx Opal Kelly USB 2.0 Ctrl Lines Valerio Bocci 2009 PIN/APD

Serial line receiver and read-out (Opal Kelly Xilinx Board) Spartan 3 FPGA Test and understand ADC serial link, data aggregation,Trigger primitives Extraction PC acquisition using USB interface

Time schedule (1) The goal is to have the first prototype boards in April 2010 End of November finalize schematics End January 2010 PCB layout End Febray 2010 mounted PCB Feb-March Test in lab

Time schedule (2) Study the possibility of connecting a few channels to the “kapton cable” of the CMS encapsulated APD’s. If OK, test use them in testbeam. If not connection to Kapton cable not possible we would like to have the possibility to test a few channels (5) with PIN diodes on Beam.