The Pentium Series CS 585: Computer Architecture Summer 2002 Tim Barto

Purpose of Presentation Give brief overview of Pentium Series line of processors Describe caching scheme used in the Pentium Processor Structure Operating modes Techniques to maintain consistency Describe integer pipelines and instruction flow

Pentium Processor Pentium Pro Processor Pentium II Processor Pentium III Processor Pentium 4 Processor Introduced 03/23/9311/01/9505/07/9702/26/9911/20/00 Operations Per Clock Cycle Max Clock Speed 60MHz system bus: 150MHz 66MHz system bus: 200MHz 60MHz system bus: 180MHz 66MHz system bus: 200MHz 66MHz system bus: 333MHz 100MHz system bus: 450MHz 100MHz system bus: 1.0GHz 133MHz system bus: 1.4GHz 400MHz system bus: 2.40GHz 533MHz system bus: 2.53GHz Bus Frequency60MHz, 66MHz 60MHz, 66MHz 66MHz, 100MHz 100MHz, 133MHz 400MHz (100 * 4), 533MHz (133 * 4) Number of Transistors 3,100,000 (0.8 micron) 5,500,000 (0.35 micron) 7,500,000 (0.35 micron) 24,000,000 (0.13 micron) 42,000,000 (0.13 micron) Summary of the Pentium Series of Processors

L1 Cache16KB 32KB 12k µop + 8KB Data L2 Cache-1MB (on chip) 512KB (off chip) 512KB (on chip) 512KB (on chip) Addressable Memory 4GB64GB Integer Pipelines Floating Point Pipelines Brief Description Superscalar architecture brought 5X the performance of the 33MHz Intel486 DX processor Intel’s first true server / workstation chip Dual independent bus, dynamic execution, Intel MMX technology Data Prefetch Logic, Level 2 Advanced Transfer Cache Capable of delivering 4.2GB of data-per- second into and out of the processor Pentium Processor Pentium Pro Processor Pentium II Processor Pentium III Processor Pentium 4 Processor Summary of the Pentium Series of Processors (continued)

Pentium Processor Successor to the Intel486 processor 16-bit based Originally introduced with a 60MHz clock speed Added a second execution pipeline to achieve two- way superscalar performance CISC instruction set

Cache Structure Has only one level of on-chip cache, L1 L1 size = 16KB Divided into two 8KB sections (one for code the other for data) Organized in a set-associative structure

Cache Operation Modes Two bits which allow for control of cache: CD (Cache Disable) NW (Not Write-Through) CD = 1, disables cache CD = 0, enables cache NW = 1, enables write-back mode NW = 0, enables write-through mode

Cache Consistency Data cache uses the MESI Protocol M (Modified) state indicates line is modified E (Exclusive) state indicates line is not modified S (Shared) state indicates line may be shared with other caches I (Invalid) state indicates line is not available in cache Code cache uses a subset of MESI Protocol Supports S (Shared) and I (Invalid) states

Cache Consistency (continued) Additional methods used to ensure cache consistency: Inquire Cycles Cache Flushing

Integer Pipelines and Instruction Flow Uses two parallel pipelines known as “U” and “V” pipes U pipe has 5 stages Prefetch (PF) Instruction Decode (D1) Address Generate (D2) Execute (E) Writeback (WB)

Integer Pipelines and Instruction Flow (continued) V pipe is similar to the U pipe but has some limitations on the instructions it can execute

Conclusion Pentium processor successfully expanded upon the Intel486’s architecture Today, the Pentium 4 continues to break new ground in processor technology For more information, check out: