CMOS 2-Stage OP AMP 설계 DARK HORSE 2401867 이 용 원 2401871 홍 길 선 Dec.06.2006 DARK HORSE 2401867 이 용 원 2401871 홍 길 선

Design Specification Table Factor Spec Supply Voltage Vdd = 3V Vss = 0V Input Common Mode Voltage 1.5V Voltage Gain > 100 dB Phase Margin > 70 degree Unity-Gain Frequency (GBW) > 50 MHz Power Consumption 30 mW Load Capacitance 20 pF PSPICE Version: 10.3 1st stage 2nd stage Total spec Gain : > 100dB Unit Gain Freq : > 50MHz Phase margin : > 60 Current : < 10mA 1st stage spec Gain : > 40dB Unit Gain Freq : ?? Phase margin : ?? Current : < 4mA 2nd stage spec Gain : > 60dB Unit Gain Freq : ?? Phase margin : ?? Current : < 6mA

Application Field - 연산기능에의 응용 - - 능동 필터로의 응용 - - 발진회로로의 응용 - 비교회로, 가감산회로, 승제산 회로, 미적분회로, 대수변환 회로 - 능동 필터로의 응용 - 능동 저역통과필더, 능동 저역통과필터, 대역통과필터 - 발진회로로의 응용 - 비안정 멀티바이브레터, 정현파발진회로, 수정발진회로, Wein브리지 발진 회로 - 비선형 회로에 응용 - 절대치회로, 슈미트회로, 삼각파-정현파 변환회로, 첨두값 홀드회로, 샘플 홀드회로 - 변조회로에 응용 - AM변조회로, PWN변조 회로, PAM회로 - 전자제품 - TV, 라디오, 오디오, 컴퓨터, 실내온도조절기, 에어컨, 전화 오실로스코우프, 항공기, 선박모니터링 시스템, 의료기기, 군사병기 등

Personal Role Task Charge 1. OP Amplifier Specification 이 용 원 / 홍 길 선 2. Bias Circuit Design 이 용 원 3. Design and Simulation for First Stage (Differential Pair) 홍 길 선 4. Design and Simulation for Second Stage (Folded Cascode) 5. Integration and Overall Simulation 6. Results Comparing 7. Documentation 8. Presentation

Used NMOS & PMOS Model Parameter (1) Used process TSMC 0.35um T44D_MM_EPI CMOS process  http://www.mosis.org/Technical/Testdata/menu-testdata.html - One MN model and one MP model are contained

Used NMOS & PMOS Model Parameter (2) Used NMOS Model Parameter: Level 49 (BSIM3) Created NMOS Model symbol

Used NMOS & PMOS Model Parameter (3) Used PMOS Model Parameter : Level 49 (BSIM3) Created PMOS Model symbol

Differential amplifier Modified folded cascode amplifier Designed Schematic CMOS Bulk connection was removed to simplify the schematic. Start Up Bias circuit 1st stage Differential amplifier 2nd stage Modified folded cascode amplifier

Designed Schematic - Bias Circuit - Well Knwon Biasing Circuit - First Block  Self Bias - Last Block  To reduce effect by differential pair  120 uA to Diff. Amp

Hand Analysis on the 1st – Differential Pair Amplifier - Refer to Sedra chapter 7.5 : Applied MOS Differential Pair with active load Analysis equations  Vo2  Vo1  120 uA from Bias Circuit

Hand Analysis on the 1st stage – Calculated Results in Excel Sheet ** Note : CL is not defined, so the f(-3dB) cannot calculated. The calculated 3dB frequency is not exact value. All equations are implemented in an excel sheet. The results are calculated in automatic The design targets for 1st stage are Gain : 40dB Unit freq : Cannot calculated.  Overall spec. is given. Calculated Result * About the value of Lamda for Rout calculation?  It’s value is calculated from the IV curve of the transistor.

Hand Analysis on the 2nd – Folded Cascode Amplifier Analysis equations - Reference : Self biased Complementary Folded Cascode

Hand Analysis on the 2nd stage – Calculated Results in Excel Sheet ** Note that : CL is assumed as 20pF, so the 3dB frequency of 2nd stage can be calculated. For decide , we just set this value as 0.5V Calculated Result The 3dB frequency is lower than 1MHz All equations are implemented in an excel sheet. The results are calculated in automatic The design targets for 2nd stage are Gain : 60dB

Hand Analysis on the Overall Schematic Analysis equations This calculation is not exact one. But 1 is lower than 2, so the 3dB frequency will be lower 1.  Calculated S is unity gain frequency (GBW) Calculated result in excel sheet

More Hand Analysis of the other specifications Analysis equations (1) OVR Vout,max = Vdd - (MP2) - (MP4) = 3V - 2    2V Vout,min = 0 + (MN5) + (MN7) = 2    1V OVR = Vout,max – Vout,min = 2V – 1V = 1V (2) Slew Rate SR = Current at final stage / Load capacitor

AC Simulation Bench in PSPICE Simulation Settings : 1. Input : Input is AC signal at plus node of amp. 2. Output load : 20pF  follows the calculation condition 3. Minus node of op amp : Feedback from the output node.  DC voltage will be supplied in automatic Large value of L blocks of signal feedback 4. Simulation frequency : 1Hz ~ 1GHz / 100point per decade in log scale. Simulation Bench

AC Simulation Results of designed OP Amp Phase vs frequency Simulation result shows that Gain : 101.08 dB Phase Margin : 62.63 180 – 117.37 = 62.63 Unit Gain Frequency : 56.23MHz 3dB Frequency : 380Hz Gain vs frequency

DC Simulation Bench in PSPICE

DC Simulation Results of designed OP Amp Simulation result shows that Total supply current : 3.15mA Supply voltage : 3V Total power consumption : 9.45mW This values are calculated with the measured result with bias Vdd = 3V

Slew Rate Simulation Bench in PSPICE Simulation Settings : 1. Input pulse : 1uS pulse width & very short rising, falling, delay time. 2. Output load : 20pF  follows the calculation condition 3. DC voltage at minus node of op amp : 1.58V  Common mode voltage 4. Simulation time : ~ 100uS  To check the several pulses Simulation Bench

Slew Rate Simulation Result in PSPICE Simulation result of Slew Rate Timing delay to 90% of Vdd is 101.31nS 90% voltage of Vdd is 2.69V (Actually we want to measure the 2.7V)\ SR = 2.69V/0.101uS = 26.6 V/us

OVR Simulation Bench in PSPICE Simulation Settings : 1. Input variation : DC sweep from 1.57V ~ 1.59V for V4 2. DC voltage at minus node of op amp : 1.58V  Common mode voltage ** The reason to sweep from 1.57 ~ 1.59 The total gain of this circuit is almost 100dB. 3V – 1.58V = 1.42V 1.42 / 100dB = 1.42 / 10^5 = 14uV So, if the 14uV at plus node is higher than that of minus, the output voltage goes to 3V We just needed narrow region of voltage sweep

OVR Simulation Result in PSPICE Output voltage Input voltage Linear region Difference is almost 1V In a calculation, we expected that this linear region lies from 1V ~ 2V, But, in this simulation, we can check that this region is from 0.95V ~ 1.95V, although value is 1V.

CMRR Simulation Bench in PSPICE Simulation Settings : 1. Input condition : AC signal is added to plus & minus node at the same time 2. Simulation frequency : 1Hz ~ 1GHz / 100point per decade in log scale. * The work of input capacitor : It is used as a DC blocking from plus to minus The value is 1F  This means that the inputs are short in AC but, these are open in DC. : We can supply a same phase signal ( common mode signal) to all inputs at the same time.

CMRR Simulation Results in PSPICE Simulation result shows that CMRR is 83.9dB The 3dB is higher than that of differential mode. This means that this circuit is isolated quite well although it’s just a simulation.

Comparison Table Spec Hand Analysis SPICE 1.5V - 1.58V 100 dB 110.2 dB Input Common Mode Voltage 1.5V - 1.58V Voltage Gain 100 dB 110.2 dB 101.08 dB Phase Margin 70 degree 88.45 degree 62.63 degree Unity-Gain Frequency (GBW) 50 MHz 58.3 MHz 56.23 MHz Load Capacitance 20 pF Follow a spec Output Voltage Swing (OVR) 1 V Slew Rate 40 V/us 26.6 V/us CMRR 83.9 dB Power Consumption 30 mW 26.88 mW 9.45 mW

Conclusion Differential Pair Apmlifier와 Folded Cascode Amplifier로 구성된 CMOS 2-stage Amplifier를 설계해 보았다. Hand analysis를 통해 대략적인 Tr의 사이즈를 정하고 Spec.을 만족하는지 확인 했다. 주어진 Spec.을 만족시키지 못하는 경우, Hand analysis을 반복했다. 이후에 시뮬레이션을 통해서 결과를 보고, Spec.을 만족 시키지 못하는 경우 사이즈를 수정하는 과정을 반복했다.이 과정을 통해서 주어진 Spec.을 만족시키는 OP Amp를 설계할 수 있었다. 설계한 OP Amp의 성능은 시뮬레이션 결과를 통해서 확인 할 수 있었다. OP amp 설계과정에서 Power, Gain, Slew Rate, GBW, CMRR, OVR등을 고려하기는 했지 만 모든 성능을 만족시키는 적당한 값을 정하는 것이 쉽지 않았다. 결국 여러 번의 simulation에 의해 spec과 유사한 성능을 가지는 OP Amp를 설계할 수 있었다. 이번 project을 통해 반도체 Chip 설계 procedure를 이해할 수 있는 계기가 되었으며 iteration을 통해 최초에 정한 spec에 가깝게 circuit을 보완해 나가는 과정을 경험 할 수 있는 좋은 기회였다.

Reference - www.mosis.org web site:    http://www.mosis.org/Technical/Testdata/menu-testdata.html          - Analysis and Design of Bipolar/CMOS/BiCMOS Analog Integrated Circuits   by Dong-Youl Jeong, Fairchild Korea Semiconductor - 전자회로 특론, 조규형 교수 著, 한국과학 기술원 - PSpice를 이용한 CMOS Amp 설계 Manual, 노정진 교수 著, 한양대학교 - A 1.8V SELF-BIASED COMPLEMENTARY FOLDED CASCODE AMPLIFIER by B. G. Song*, **, O. J. Kwon*, I. K.Chang*, H. J. SONG* and K. D. Kwack* - Microelectronics Circuits, Sedra Smith, Fifth Edition - Lecture Materials