2 s 2.org 2008 MSD Annual Review Simulation study and tool development for ultra-scaled InAs HEMTs Theme 6 Neerav Kharche, Mathieu Luisier, & Gerhard Klimeck Purdue University, West Lafayette MSD Annual Review Novel devices beyond Si CMOS Robert Chau, Intel Research III-V HEMTs/MOSFETs  recently emerged as potential candidates for high- speed, low-power logic  Need to develop modeling approaches to aid experiments and to explore novel designs Device structure and modeling approach 2-D Schrödinger-Poisson Solver Real-space effective mass quantum transport model Injection (white arrows) from Source, Drain, and Gate contacts Calibration to existing experimental data Adjust parameters within experimental uncertainties to match low V g regime Fitting parameters  Gate length L g  Gate work function Φ m  Insulator thickness t ins  Tunneling effective masses through InAlAs m y ox and InGaAs m y buff Effective masses in the channel are extracted from tight-binding calculation Use experimentally measured R S, R D to obtain complete I d -V g Strained InAs InAlAs ΦMΦM Drain InGaAs m y ins t ins m y buf m x,z mymy LgLg Fitted to tight-binding bandstructure Gate Source Experimental Devices: III-V HEMTs for Logic Applications (D.H. Kim et. al, IEDM 07, EDL 08) Optimized parameters and I d -V g comparison ParameterInitial30nm40nm50nm Lg [nm]30, 40, t ins [nm] m y ins m y buf Φ m [eV] R sd [Ω.mm]0.21,0.24 L g = 30nm L g = 40nm L g = 50nm Extracted device parameters L g [nm]Vt Vd=0.05 Vt Vd=0.5 S [mV/dec]DIBL [mV/V] I ON /I OFF v inj [cm/s] x x x x x x x10 7 Evaluation methodology proposed in R.Chau et. al. (T-Nano 2005) is used Device metrics  Black: simulated Id-Vg  Red: experimental Id-Vg Good matching with experimental I d -V g is achieved for devices with 3 different gate lengths Simulator can be used to study scaling behavior of nanoscale InAs HEMTs Plan to study scaling behavior and explore device design optimizations Gate leakage current distribution Gate leakage current is concentrated at the edges of the gate contact Edge geometry plays an important role in determining gate leakage current Bias: low V g high V d Design optimization: gate work function engineering Higher Φ m shifts V t in +ve direction Reduces gate leakage Subthreshold slope, DIBL and g m,max unaffected Φ M [ eV] VT 0.05 [eV] VT 0.5 [eV] S [mV/dec] DIBL [mV/V] I OFF [A/m] I ON [A/m] I ON /I OFF g m,max V d =0.05V V d =0.5V Tool deployment on nanoHUB.org Effect of geometrical parameters such as gate length L g, insulator thickness t ins, Channel thickness t channel etc can be analyzed Material parameters Wide variety of materials can be simulated by supplying appropriate material parameters IV characteristics Electron injection is done from Source, Drain & Gate contacts Simulates various transfer characteristics  I d -V g  I g -V g  I d -V d  I g -V d In-depth insight into device operation Electrostatic potential Electron distribution y-component of gate leakage current in OFF state Summary Effective mass based 2-D Schrödinger-Poisson Solver to simulate III-V HEMTs is presented Injection from Source, Drain, and Gate contacts modeled Study gate-leakage current Simulator is verified against the experimental measurements on InAs HEMTs (good quantitative match) Ongoing work: optimize the design of 20nm III-V HEMTs The tool ‘omenHFET’ will be deployed on nanoHUB.org The use of the nanoHUB.org computational infrastructure operated by the Network for Computational Nanotechnology and funded by the National Science Foundation is gratefully acknowledged