Hybridization, interconnection advances Massimo Manghisoni Università degli Studi di Bergamo INFN Sezione di Pavia December 17, 2015

Motivations  Experiments at the future high luminosity colliders set challenging requirements on the design of semiconductor pixel detectors  Designers are currently considering two different approaches: moving to higher density 2D technology nodes moving to 3D technologies with vertical integration techniques  3D integration is a technology that makes it possible to devise pixels with advanced architectures smaller form factor less material and dead areas separation of sensing, analog and digital function  Features of 3D integration can be applied to Particle tracking: wide interest in the high energy physics (HEP) community in view of the design of novel pixel detector systems with advanced readout electronics X-ray imaging: development of advanced X-ray imaging instrumentation for applications at the free electron laser (FEL) facilities 2 of 25

Outline Focus of the talk: R&D activity on advanced interconnections  The AIDA 2020 Collaboration (WP4)  Pixel modules for tracking at HL-LHC  High-resolution imagers for photon science application  Medipix - CERN  VIPIC - Fermilab  PixFEL Project - INFN 3

AIDA WP4 - Task 4.4 Interconnections and TSVs  CERN, INFN (GE, PV, PG), CNRS (CPPM, LAL) MPG-MPP, UBONN, UNIGLA  Coordination: INFN Bonding and TSV technologies  Qualification of Industrial bonding techniques: requirements of future HEP experiments addressed in terms of  pixel readout cell pitch (order of 20 μm) and geometry  interconnection density  Etching TSV in fully processed 65 nm CMOS wafers for peripheral backside interconnections: the baseline TSV technology will be “via last”  Explore processes for relatively fine pitch TSVs in thinned CMOS wafers, which will also include chip backside processing steps

LHC Hybrid pixel modules 5 FEIxSensor FlexWire-bond Stave surface FEIx Sensor FlexWire-bond Stave surface Standard pixel modules Wire bonds are the weak link  Oscillation in magnetic field  Protection required or desired  Limit on envelopes  Require flex to be glued very precisely  Access to bond area on FEIx limits the sensor active area (not 4-side buttable) Modules without wire-bonds Reverse sensor and FEIx order  Better controlled envelopes  Sensor can be larger than FEIx size and is 4-side buttable  No fragile wire bonds needed  Sensor cooled directly by stave

Enabling Technologies 6 FEIx Sensor Flex Wire-bond Stave surface TSV-last + RDL For Flex to FEIx connection  Connect chip M1 from front to back of chip  RDL distributes all FEIx connections over full chip surface Do not need fine-pitch connections Power can be brought to chip at several places, not just on the edge Direct laser soldering for flex to chip connection  Thin 2-layer Al flex  No glue layer needed  Connections are solder 1-by-1, module stays at RT  Reworkable leti CEA-LETI

Direct laser soldering 7 Flex is thin 2-layer Al on Kapton flex with Solder ball (200  m) inside which is melted by laser  No module heat up & No thermal stress on module No glue is needed between flex and bare module  Solder holds flex mechanically well in place 7 9 MAPS solder to flex (50 µm thick chips, 15x30mm2 each chip) 27 cm long P. Riedler, A. Di Mauro, A. Junique (PH-AID ALICE)

LETI TSV+RDL 8  Medipix & LETI developed TSV on Medipix IBM chip to allow for BGA assembly for buttable X-ray/particle detectors  Second run processed 6 wafers of Medipix3rx : TSV yield ~ 70% to 80% Design Process Flow Medipix specifications Single chip Wafer view Test structures  Wafer diameter: 200mm  Wafer thickness: ~725um  IC Technology: 130 nm / IBM  Top Surface: Al + Nitride  Chip size : x µm  TSV per chip: ~100  TSV aspect ratio : 120:60 µm (MEDIPIX RX) 50: 40 µm (timepix3) M.Campbell /CERN-PH – G.Pares / CEA-LETI

Activity μm 150 μm or less TSVs module Bonding … front end chip (65 nm) back side front side sensor HV The Ultimate Goal New (LETI Proprietary) Bump Bonding Collaboration: CERN, Glasgow, LAL & MPI  Flip chipping at LETI FEI4 B + Sensor, Satisfactory results (prototype irradiated and Beam tests..)  Start With FEI4, TSV + RDL  The Future: Build a demonstrator: TSVs in a 65 nm front-end chip (from RD53 engineering run)

Direct Wafer-to-Wafer bonding 10 Requires  Post processing at wafer level to produce smooth surfaces  Matching wafer size  Excellent alignment  TSVs to bring front signal to backside Allows  Thin devices (Process as a single wafer after bonding)  TSVs to be added after the bond  Minimizes bond cap/inductance Bond sensor wafer directly to FE wafer Remove single die flip-chip process Cu-Cu / SiO 2 -SiO 2 and hybrid bonding Direct bond formed between 2 wafers bond Cu & Cu / SiO 2 & SiO 2 Requires smooth and activated wafer surfaces (Roughness ~ 0.5 nm) Room temperature and room pressure bond process CEA-LETI Demonstrated direct bonding Cu-Cu, SiO 2 -SiO 2 and more complex Hybrid bonding Wafer-Wafer assembly Thin ROC wafer is “fused” to sensor wafer

Bonn/CPPM TSV project Goal of the project: develop modules for ATLAS pixel detector at the HL-LHC using a via last TSV process  Post-processing technology applicable on existing FE electronics  Dead area at the chip periphery can be reduced  Compact, low mass hybrid pixel modules with minimal modification to the FE layout and using standard CMOS technology  no wire bonds needed if combined with new flex hybrid interconnection  Potential for 4 side abuttable modules using dedicated sensor layout Modules with TSV can be used for the outermost detector layers at the HL- LHC to provide full detector coverage over the large area 11

Via last TSV at IZM  Process: IZM via last tapered TSV  Demonstrator single chip modules built with:  FE-I2/3 ATLAS pixel readout chip 90μm thin, with tapered profile TSV and RDL  Planar n-in-n sensor  Standard flip chip process (no handle wafer for thin chip handling used, unconnected pixels expected along the chip perimeter)  No loss in performance wrt modules without TSV 12

C2C SLID (Solid Liquid Inter-Diffusion)  Bump-less interconnect  smaller pitch -> finer pixel for hybrid detectors  less material – no bumps  The most prominent way: SLID (Solid Liquid Inter-Diffusion)  So far mostly W2W, or C2W with re-composition of chips on support wafer  C2C is very attractive during R&D but also production (very different chips..)  Final goal: replace bumped flip-chip with C2C SLID interconnect to thin ASICs 13 R&D activity from MPP/EMFT

3D integration in Photon science Medipix3 chip  256 X 256 pixels on a pitch of 55μm  130 nm CMOS technology  I/O wire bonding pads compatible with TSV technology  TSV=connections between front and back sides of the ASIC  CERN-LETI collaboration (TSV Last developed by LETI and applied to pixel detector read- out chip designed and supplied by CERN) VIPIC1 Demonstrator  64 X 64 pixels on a pitch of 80 μm  130 nm CMOS technology PixFEL Project  64 X 64 pixels on a pitch of 100 μm  65 nm CMOS technology 14

VIPIC1 Vertically Integrated Photon Imaging Chip 15 Detector  Si d=500  m, pitch 80×80  m 2, soft 8keV X-rays Application  XPCS (X-ray Photon Correlation Spectroscopy) Electrically testable using  wire bonded connections  bump-bonded connections Tests in configuration with  Sn-Pb bump-bonded sensor  Fusion-bonded sensor (Low-Temp. Direct bonding) 3D technology providers  Tezzaron  Ziptronix. Collaborating institutions Fermilab, AGH-UST, BNL  Cu-DBI (oxide-oxide fusion bonding) used for bonding tiers of 3D VIPIC  8” bonded wafer pair with top wafer thinned to expose 6  m TSVs (6  m of silicon left of the top wafer) W2W tier stacking D2W ASIC-sensor LTD-bonding  Ni-DBI (oxide-oxide fusion bonding)

LTD-bonded vs b-bonded 16 LARGE FEEDBACK RESISTANCE ENC=36.2 e - ± 2.6  V/e - symmetrical noise distribution with <3.4 % of pixels outside of ±3  range competitive to MAPS! 32 × 38 pixels bonded, 2880 pixels floating bump-bonded: ENC=69.6 e - ± 5.1  V/e - larger input capacitance = larger noise, lower gain and more dispersions Bump-bonded VIPIC1 pitch 100  m vs. 80  m for fusion-bonded, nevertheless … ENC on fusion bonded device is close to that measured for floating inputs! ENC=40e - C in 80fF

From VIPIC1 to VIPIC-Large: 1Mpixel XCS Detector 17 X-ray back-side illumination Features  1Mpixel = 3 shingles of 6×2 or straight 7×7 VIPICs-L LTD-bonded (D2W) to a sensor wafer  No dead edges, no peripheral circuitry on the ASIC  65  m - pitch square pixel, 36,864 pixels/chip grouped in indiv. readout subchips of 1024 pixels  1 FPGA per VIPIC-L for on the fly data processing (up to 0.7 Tbps of raw data produced)  Multi-layer (>20 routing layer LTCC) supports b-bonded detector structure  Flat back-side - friendly for mounting of a cooling plate

B-TSV 18 Via-Last TSVs (inserted in post- processing after thinning of a 3D bonded wafer pair)  B-TSV (requirement: identical DRC as GF TSVs) Work with Tezzaron/Novati on B-TSVs  Bosch etching used for B-TSV cavities and internal metal (M1) is Cu - DRC rules = GF TSV rules - 2 3D-integrated wafer pairs tested TSVs are critical component for VIPIC-Large  small diameter ~1  m TSVs  wire-bond-less  no-dead-zone Middle Bottom Top 1470A469A Oxide SiN TEOS SiN

B-TSVs – capacitance and resistance 19 B-TSV to substrate capacitance TSVs to substrate breakdown voltage measurement:  W#5 V BREAK =38.5V ± 9V  W#6 V BREAK =36.5V ± 5V B-TSV resistance Single B-TSV resistance is a difference between 1TSV/connection and 2TSV/connection  . Wafer #6 showed more defective B- TSV in the chains 1TSV 2TSVs

VIPIC-L Design Highlights 20 New approach for entirely edgless design – enabled by 2 tier 3D integrations  array of pixels on the analog tier  whole digital tier P&R-ed at once without respecting pixel boundaries 32 × 32 VIPIC-L analog pixels forming single analog tier subchip (6 ×6 subchips form one full analog tier chip) Digital tier chip designed in 130nm process; next design is clearly 65nm or beyond 32 × 32 pixels VIPIC-L digital tier subchip with no explicit boundaries of pixels

The PixFEL Project 21  Long term goal: Develop a four-side buttable module for the assembly of large area detectors with no or minimum dead area to be used at FEL experiments  Collaboration: INFN (PV,PI,TN) UniPV, UniPi, UniBI, UniTN Multilayer device: active edge thick pixel sensor, two tiers 65 nm CMOS readout chip (analog+digital/memory) with low/high density TSV, pixel pitch of 100 mm

Demonstrator Sensing layer - front-end chip: relatively large pitch of 100um easily achieved through bump-bonding techniques Through silicon vias (TSVs) to access the circuits from the back side and including substrate thinning 3D integration to interconnect the analog front-end and ADC on one tier to the memories on the other tier 22 Main features  32x32 array of hybrid pixels  three-tier structure  slim edge, fully depleted silicon sensor  two-tier readout chip, in 65 nm CMOS technology  1 layer with analog front-end and ADC  1 layer devoted to digital memory Interconnection and vertical integration

Summary  Pixel detector requirements for next generation experiments at high luminosity colliders and X-ray sources are extremely challenging high granularity → small room for electronic high hit rate → high speed, on-chip memory data reduction → hit discrimination capability radiation hardness  More functionalities need to be built into the readout chip to satisfy the specifications front-end performance improvement data selection and hit discrimination (bandwidth reduction) 23 3D integration technologies may provide several advantages in the design of detectors for vertexing and imaging applications