Training LHC Powering Robin Lauckner Software Tools for Commissioning Robin Lauckner 28 th March, 2007

Training LHC Powering Robin Lauckner2 Summary Control System Architecture Sequence of Tests for Commissioning Overview of the Software Circuits, SOCs and Tests in the Control System Applications –Sequencer –SOC editor –Circuit synoptic –Post Mortem Analysis (PMA). People roles and authorisation

Training LHC Powering Robin Lauckner3 Control of a circuit Quench Detector Quench Heater PS PIC Quench Detector Quench Heater PS Power Converter Energy Extraction QPS Controller Quench Detector FGCFGC SCADA SERVERS APPLICATION SERVERS PM SERVERS OPERATOR CONSOLES Tunnel UA83 SR8 CCC WORLDFIP Bus Ethernet WORLDFIP Front End PLC

Training LHC Powering Robin Lauckner4 Sequence of Commissioning Tests There are three main phases for cold circuit commissioning 1.Short Circuit Tests - warm 2.Interlock Tests – during and after cooldown 3.Powering to Nominal - cold Phases consist of several tests that may vary depending on the circuit under test The short circuit tests are the same for all cold circuits except the 60A orbit correctors that are powered for a shorter time. The interlock tests to be performed on a circuit depend on the interlock type, (see M. Zerlauth). Interlock type depends on the hardware interfaces between the PIC, PC and QPS systems. The sequence of tests during powering to nominal depends on the circuit type, (see R. Schmidt). Circuit type depends on the energy stored in the electrical circuit, and way of protecting magnets and current leads

Training LHC Powering Robin Lauckner5 PC QPSPICPC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT DISCHARGE_REQUEST PC_DISCHARGE_REQUEST Interlock Type A (=13kA main + IT) QPSPICPC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PC_FAST_ABORT Interlock Type B1 (=600A EE, 600A no EE, 600A no EE crowbar + all dipoles of IPQD) QPSPICPC CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT_B2 PC_FAST_ABORT Interlock Type B2 (=all quads of IPQD) PICPC POWERING_FAILURE PC_PERMIT Interlock Type C (= A) Interlock Types PC_PERMIT_B1 Markus Zerlauth

Training LHC Powering Robin Lauckner6 Sequence of Interlock Tests Test NameInterlock Type AB1B2C PC_PERMITxxxx POWERING_FAILURExxxx CIRCUIT_QUENCH_VIA_QPSxxx PIC_FAST_ABORT_REQUEST_VIA_PICxxx PC_DISCHARGE_REQUEST_VIA_PCx PIC_DISCHARGE_REQUEST_VIA_PICx

Training LHC Powering Robin Lauckner7 Superconducting Circuit Types 13 kA Main: Main dipoles and main quadrupoles (24 circuits) IT: Inner triplet quadrupoles (8 circuits) IPQD: Individual powered insertion main magnets (94 circuits) Extraction of the energy stored in the magnets is performed by the QPS system 600 A EE:most 600 A corrector magnets powered in series (202 circuits) Extraction of the energy stored in the magnets is performed with an energy extraction unit back to back to the power converter rack 600 A no EE crowbar: most individual 600 A trim quadrupoles (136 circuits) Extraction of the energy stored in the magnets is performed with the power converter 600 A no EE: inner triplet correctors (56 circuits) No energy extraction unit required A: 80 A and 120 A (300 circuits) No energy extraction unit required, connected to the Powering Interlock Controller 60A: 60 A (752 circuits) No energy extraction unit required, not connected to the Powering Interlock Controller Rüdiger Schmidt

Training LHC Powering Robin Lauckner8 Sequence of Powering Tests

Training LHC Powering Robin Lauckner9 Goals of the Commissioning Software Two goals to achieve during cold circuit commissioning are: Key features for meeting these goals are: Drive each circuit through the appropriate sequence of tests Identify any non-conformity of the protection systems before it becomes critical The data describing the circuits and the commissioning tests in the operational database A task sequencer that executes validated tests reproducibly Software for analysis of tests results so that experts and operators can make the correct interpretations and decisions after each test. The control software for circuit commissioning aims to help the operator reach these goals while performing the tests efficiently.

Training LHC Powering Robin Lauckner10 Control System View of a Circuit Each LHC circuit has a description in the operational database. A circuit has a name, a circuit type, an interlock type, the name of the last test passed, the short circuit status, a flag indicating that the circuit is locked (and may not be powered). Tests that are not to be run on this circuit are also defined – cancelled tests This information is used to manage the sequence of tests of this circuit and it is important that the responsible people ( not database team) maintain the data accurately. Design and test data are also stored for each circuit: I_NOMINAL, I_INTERIM1, … Circuit Name Circuit type Interlock type Last test passed Short status Is locked Cancelled tests UA 83 Quench Detector Quench Heater PS PIC Quench Detector Quench Heater PS Power Converter Tunnel Energy Extraction QPS Controller Quench Detector Arc cryostat DFBAO

Training LHC Powering Robin Lauckner11 Set of Circuits - SOC SOCs are collections of, 1 or more, circuits that are represented by attributes in the operational database. SOCs are created, deleted or edited freely. Each SOC has its own name, the names of the member circuits and records to indicate whether it is operational and whether a console has reserved the SOC for running tests. Operational SOCs are logged and have fixed displays made available. During commissioning tests are performed on SOCs. The circuits in a reserved SOC may not be used by other consoles. SOC Name Circuits Operational Reserved

Training LHC Powering Robin Lauckner12 Control System View of a Test Test Name Order Short Status Circuit types Interlock Types Tests are also stored in the operational database. Their attributes are the test name, the order in the sequence of tests, which short status is required, and the circuit types and interlock types for which the test is applied. Not all tests are known in the control system (entered in operational database). Some are known but no procedure is defined and the test is performed manually – “hurdles”. Such tests usually concern many circuits i.e. CRYO_START is TRUE, which pertains to Powering Subsector.

Training LHC Powering Robin Lauckner13 Context and Data Flow LHC Functional Layout DB (Machine Layout) LSA DB (Operational Data) Set of Circuits Circuit Information Test parameters Test plan (tests done / to be done) Test outcome (success/failure) MTF DB (Assets) Test Software Journals, Analysis (files) [ upload every 2 h] Circuit Information, design data [ changes copied once / day ] [ created after each test ] [ after each test ] [ before each test ] MTF sequence, step names [ updated manually on change ] Vito Baggiolini Machine Layout Assets control Configuration Operational Data Ronny Billen

Training LHC Powering Robin Lauckner14 Automated Test Procedures (Sequencer) PVSS-CMW Interface ETHERNET PVSS-CMW Interface CMW WorldFIP PC_DISCHARGE_ REQUEST QPS Power Converter PC_PERMIT PC_FAST_ABORT POWERING_FAILURE PIC CIRCUIT_QUENCH DISCHARGE_ REQUEST Operational DB Interacting with the systems PM Data PVSS Supervision Front Ends Markus Zerlauth

Training LHC Powering Robin Lauckner15 The Sequencer The Sequencer executes sequences of tasks Essential tool for commissioning and operating LHC –Guides operators through sequences of tasks –Executes sequences manually (step by step / task by task) or automatically What is the Sequencer? The sequencer executes on a central server, it can execute sequences launched and monitored by multiple consoles The sequencer creates a journal and informs operator of execution status The sequencer supplies GUI panels specifically developed for hardware commissioning, these display SOCs, circuits and tests The sequencer reads the sequence of tests from the operational database Features Sequencer Sequence = Commissioning Test

Training LHC Powering Robin Lauckner16 Sequencer GUI – operator view

Training LHC Powering Robin Lauckner17 Sequencer GUI – code view

Training LHC Powering Robin Lauckner18 The SOC Editor The SOC editor creates and edits SOCs It is the tool for organising the commissioning work each day The SOC editor also edits the electrical circuit information held in the operational database The sequencer runs tests on SOCs What is the SOC Editor? Provides a powerful search interface for assembling sets of circuits Allows the operator to manage console reservations and the operational status of the SOCs Protected access to Short Status, Locking, Cancelled Tests and the Last Test Passed pointer The same methods are used by the SOC editor and the sequencer to establish the sequence of tests for each circuit Features

Training LHC Powering Robin Lauckner19 SOC Editor Create GUI A Set of Circuits is being created for the commissioning of the circuits of interlock type B2 whose power converters are located in UJ63. These circuits have completed the 24 Hour Heat run and been equipped with low current shorts ready for the PIC1 tests.

Training LHC Powering Robin Lauckner20 SOC Editor and Sequencer - Setting up The SOC has been made operational to start logging services and reserved by a console. The sequencer offers 1 test from the sequence of tests for RQ10.L6. Circuits are tested one at a time

Training LHC Powering Robin Lauckner21 SOC Editor – Editing Circuit Information After a test failure the circuit is locked and may not be powered again. Mr. Circuit privileges are required to unlock the circuit. At present this action is not critical but later in the commissioning authorisation will be checked.

Training LHC Powering Robin Lauckner22 The Circuit Synoptic The Circuit Synoptic gives a commissioning overview of the LHC electrical circuits A panel monitors the interactions between the QPS equipment, the PIC and the Power Converters in a circuit From this monitor the operator can drill down to the supervision of the QPS and PIC and also access a web page displaying the PC controller What is the Circuit Synoptic?

Training LHC Powering Robin Lauckner23 Analysing Tests During PIC tests the circuit synoptic is used for on-line monitoring of circuits Periodic data for long term storage is stored in the Logging Database and can be recalled by the generic browser – Timber More detailed periodic data is stored for a week in the Measurement Database and can be browsed with – Meter Transient data is collected on the Post Mortem Server A series of tools is under development for Post Mortem analysis of periodic and transient data after aborts of electrical circuits These tools, so-called PMA, are being adapted and used for analysis of PIC tests

Training LHC Powering Robin Lauckner24 PMA Display For each commissioning test during PIC1 a fixed set of signals has been retrieved and displayed using the PM Analysis tools. The display has windows for analogue and digital signals. On the left is the result of a Powering Failure test. The sequence provoked a powering failure in the converter. The operator must check the signal transactions following this action and comment. This data is stored in the control system and sent to the MTF as an image file by the sequence.

Training LHC Powering Robin Lauckner25 The SOC Editor Functions & Rights 1.Specification of new SOCs FE 2.Create new SOCOP 3.Edit existing SOCOP a)Release reservation b)Change operational status c)Delete SOC d)Add / remove circuits 4.Edit Electrical Circuits a)Set short statusFE b)Lock a circuitOP c)Unlock a circuitMrC, EIC 1 d)Set last test passedMrC, FE 2 e)Add / remove testMrC Footnotes 1 EIC should not perform this action if locking results from analysis criterion failure 2 FE should only report 24 hrs run to enable PIC1 to start Under discussion

Training LHC Powering Robin Lauckner26 Glossary Explained here: Circuit, Control System view Circuit Synoptic Post Mortem Analysis Sequence of Tests Sequencer, sequence SOC Editor SOC, set of circuits Test, Control System view More information can be found here: and in SACEC Minutes: