1. Sequential Circuit Design Section 5-5

2. 2 State Machines Design Procedure 1.Specification- obtain (produce) problem description 2.Formulation - Obtain a state diagram or state table 3.State Assignment - Assign binary codes to the states 4.Flip-Flop Input Equation Determination a)Select flip-flop types b)Derive equations of inputs to the flip-flops from next state entries in the table

3. 3 State Machines Design Procedure (continued) 5.Output Equation Determination - Derive output equations from output entries in the table 6.Optimization - Optimize the equations 7.Technology Mapping – a)Find circuit from equations b)Map to flip-flops and gate technology 8.Verification - Verify correctness of final design

4. 4 State Machines Design Procedure; Example: Sequence Recognizer Specification Example 5-3 (pp. 233-235) 1.Specification- obtain (produce) problem description  Circuit has input, X, and output, Z  Recognizes sequence 1101 on X  Specifically, if X has been 110 and next bit is 1, make Z high

5. 5 Understand the problem specifications: Sequence Recognizer  Sequential machine recognizes the sequence 1101  The sequence 1111101 contains 1101 Sequential machine must remember that the first two one's have occurred as it receives another bit.

6. 6 Understand the problem specifications: Sequence Recognizer II  Also, the sequence 1101101 contains 1101 as both an initial subsequence 1101101 final subsequence 1101101  The sequence 1101 must be recognized each time it occurs in the input sequence.

7. 7 State Machines Design Procedure; Example: Sequence Recognizer Formulation 2.Formulation - Obtain a state diagram or state table  States remember past history Must remember we’ve seen 11 as machine receives another bit Must remember we’ve seen 110 when another bit comes along There is more to remember….  Tell me one necessary state

8. 8 Beginning State System starts in some state, A A

9. 9 If 1 appears, move to next state B B recognizes (remembers) that 1 was received Input / Output First 1

10. 10 Second 1 New state, C C remembers that 11 was received

11. 11 Next a 0 If 110 has been received, go to D D remembers that 110 was received Next 1 will generate a 1 on output Z

12. 12 What else? What happens to arrow on right? ♦ Must go to some state. ♦ Where? Remember we’ve just seen 01

13. 13 Possibility 1 We’ve just seen 01 Possibility 1: ♦ This is the beginning of new 1101; after 0 1 we get 1 01 (0 11 01) If this is the case; then:

14. 14 Possibility 2 We’ve just seen 01 ♦ After 01 we get the sequence 111 (01111) NOT 101 (01101)

15. 15 You must cover every possibility You must have every possibility out of every state In this case, just two possibilities: X = 0 or 1 We fill in other cases on the white board

16. 16 Fill in Remembers that {a “11” sequence occurred } Remembers that {a single “1” sequence occurred } Remembers that a {“110” sequence occurred}

17. 17 Answer Remembers: No proper sub-sequence of the sequence 1101 has occurred

18. Chapter 5 - Part 2 18 Recognize 1101 (continued)  The states have the following abstract meanings: A: No proper sub-sequence of the sequence has occurred. B: The sub-sequence 1 has occurred. C: The sub-sequence 11 has occurred. 1/1 AB 1/0 C D 0/0

19. Chapter 5 - Part 2 19 Example: Recognize 1101 (continued I) D: The sub-sequence 110 has occurred. The 1/1 on the arc from D to B means that the last 1 has occurred and thus, the sequence is recognized. 1/1 AB 1/0 C D 0/0

20. 20 Find State Table

21. 21 3. State Assignment  Each of the m states must be assigned a unique binary code Sequence Recognizer: m=4 (A, B, C, D)  Minimum number of bits required is n such that n ≥ log 2 m where x is the smallest integer ≥ x  In general, there can be 2 n - m unused states

22. 22  # of needed codes = m = 4;  How may assignments of codes are possible with 2 bits?  4  3  2  1 = 24 State Assignment for the Sequence Recognizer: Example 5-5 p. 239

23. 23  Let us choose the code assignment : A = 0 0, B = 0 1, C = 1 1, D = 1 0  The resulting coded state table: State Assignment – (continued) Present State Next State x = 0 x = 1 Output x = 0 x = 1 0 0 100 0 1 00 1 01 00 1 00 0 101

24. 24 4. Find Flip-Flop Input and Output Equations  Assume D flip-flops, outputs labeled A, B  Obtain K-maps for D A, D B, and Z: B A X 0 0 0 0 11 1 0 DADA B A X 1 0 1 0 10 1 0 DBDB B A X 1 0 0 0 00 0 0 Z

25. 25 6. Optimization:  Performing two-level optimization: D A = AB + XB D B = X Z = XAB B A X 1 0 0 0 00 0 0 B A X 1 0 1 0 10 1 0 B A X 0 0 0 0 11 1 0 DADA DBDB Z

26. 26 7. Map Technology  D A = AB + XB D B = X Z = XAB  Initial Circuit: Clock D D C R B Z C R A X Reset

27. 27 Mapped Circuit - Final Result Clock D D C R B Z C R A X Reset Library:  D Flip-flops with Reset  NAND gates with up to 4 inputs and inverters