1. 1 ALU for Computers (MIPS) design a fast ALU for the MIPS ISA requirements ? –support the arithmetic/logic operations: add, addi addiu, sub, subu, and, or, andi, ori, xor, xori, slt, slti, sltu, sltiu design a multiplier design a divider

2. 2 Review Digital Logic Gates: Combinational Logic

3. 3 Review Digital Logic PLA: AND array, OR array

4. 4 Review Digital Logic

5. 5 A D latch implemented with NOR gates. A D flip-flop with a falling-edge trigger.

6. 6 DQ CLK Value of D is sampled on positive clock edge. Q outputs sampled value for rest of cycle. Q Review Digital Logic D

7. 7 module ff(D, Q, CLK); input D, CLK; output Q; reg Q; always @ (posedge CLK) Q <= D; endmodule Correct ? module ff(D, Q, CLK); input D, CLK; output Q; always @ (CLK) Q <= D; endmodule Module code has two bugs. Where? Review: Edge-Triggering in Verilog

8. 8 If Change == 1 on positive CLK edge traffic light changes 1 0 0 R Y G If Rst == 1 on positive CLK edge R Y G = 1 0 0 CLKChange Rst R Y G (red) (yellow) (green)

9. 9 Change == 1 R Y G 1 0 0 R Y G 0 0 1 R Y G 0 1 0 Rst == 1

10. 10 R Y G 1 0 0 0 1 00 0 1 Change == 1 R Y G 1 0 0 R Y G 0 0 1 R Y G 0 1 0 Rst == 1 Change

11. 11 Change == 1 R Y G 1 0 0 R Y G 0 0 1 R Y G 0 1 0 Rst == 1 “One-Hot Encoding” DQDQ DQRGY

12. 12 Next State Combinational Logic DQDQ DQ RGY Change Rst Change == 1 R Y G 1 0 0 R Y G 0 0 1 R Y G 0 1 0 Rst == 1

13. 13 wire next_R, next_Y, next_G; output R, Y, G; DQDQ DQRGY ??? State Elements: Traffic Light Controller

14. 14 module ff(Q, D, CLK); input D, CLK; output Q; reg Q; always @ (posedge CLK) Q <= D; endmodule DQ CLK Value of D is sampled on positive clock edge. Q outputs sampled value for rest of cycle.

15. 15 DQDQ DQRGY State Elements: Traffic Light Controller ff ff_R(R, next_R, CLK); ff ff_Y(Y, next_Y, CLK); ff ff_G(G, next_G, CLK); wire next_R, next_Y, next_G; output R, Y, G;

16. 16 Next State Logic: Traffic Light Controller Next State Combinational Logic next_Gnext_Rnext_YRGY Change Rst wire next_R, next_Y, next_G; assign next_R = rst ? 1’b1 : (change ? G : R); assign next_Y = rst ? 1’b0 : (change ? R : Y); assign next_G = rst ? 1’b0 : (change ? Y : G);

17. 17 wire next_R, next_Y, next_G; output R, Y, G; assign next_R = rst ? 1’b1 : (change ? G : R); assign next_Y = rst ? 1’b0 : (change ? R : Y); assign next_G = rst ? 1’b0 : (change ? Y : G); ff ff_R(R, next_R, CLK); ff ff_Y(Y, next_Y, CLK); ff ff_G(G, next_G, CLK);

18. 18 Logic Diagram: Traffic Light Controller Next State Combinational Logic DQDQ DQ RGY Change == 1 R Y G 1 0 0 R Y G 0 0 1 R Y G 0 1 0 Rst == 1

19. 19 ALU for MIPS ISA design a 1-bit ALU using AND gate, OR gate, a full adder, and a mux

20. 20 ALU for MIPS ISA design a 32-bit ALU by cascading 32 1-bit ALUs

21. 21 ALU for MIPS a 1-bit ALU performing AND, OR, addition and subtraction If we set Binvert = Carryin =1 then we can perform a - b

22. 22

23. 23 ALU for MIPS include a “less” input for set-on-less-than (slt)

24. 24 ALU for MIPS design the most significant bit ALU most significant bit need to do more work (detect overflow and MSB can be used for slt ) how to detect an overflow overflow = carryin{MSB} xor carryout{MSB] overflow = 1 ; means overflow overflow = 0 ; means no overflow set-on-less-than slt $1, $2, $3; if $2 < $3 then $1 = 1, else $1 = 0 ; if MSB of $2 - $3 is 1, then $1 = 1 ; 2’s comp. MSB of a negative no. is 1

25. 25 ALU for MIPS a 1-bit ALU for the MSB Overflow =Carryin XOR Carryout

26. 26 A 32-bit ALU constructed from 32 1-bit ALUs

27. 27 A 32-bit ALU with zero detector

28. 28

29. 29 A Verilog behavioral definition of a MIPS ALU.

30. 30 ALU for MIPS Critical path of 32-bit ripple carry adder is 32 x carry propagation delay How to solve this problem –design trick : use more hardware –design trick : look ahead, peek –carry look adder (CLA) CLA ab cout 00 0nothing happen 0 1 cin propagate cin 1 0 cin propagate cin 1 1 1 generate propagate = a + b;generate = ab

31. 31 ALU for MIPS CLA using 4-bit as an example two 4-bit numbers: a3a2a1a0, b3b2b1b0 p0 = a0 + b0; g0 = a0b0 c1 = g0 + p0c0 c2 = g1 + p1c1 c3 = g2 + p2c2 c4 = g3 + p3c3 larger CLA adders can be constructed by cascading 4- bit CLA adders other adders: carry select adder, carry skip adder

32. 32 Design Process Divide and Conquer –using simple components –glue simple components together –work on the things you know how to do. The unknown will become obvious as you make progress Successive Refinement –multiplier design –divider design

33. 33 Multiplier paper and pencil method multiplicand0110 multiplier1001 0110 0000 0110 0110110 product n bits x m bits = m+n bits binary : 0 place 0 1place a copy of multiplicand

34. 34 Multiply Hardware Version 1 multiplicand shift left 64 bits shift right 64-bit ALU multiplier product write control 64 bits 32 bits x 32 bits; using 64-bit multiplicand reg. 64 bit ALU, 64 bit product reg. 32 bit multiplier ADD Check the right most bit of M’r to decide to add 0 or multiplicand Control provides four control signals

35. 35 Multiply Algorithm Version 1 1. test multiplier0 (i.e., bit0 of multiplier) 1.a if multiplier0 = 1, add multiplicand to product and place result in product register 2. shift the multiplicand left 1 bit 3. shift the multiplier right 1 bit 4. 32nd repetition ? if yes done if no go to 1.

36. 36 Multiply Algorithm Version 1 Example iter. step multiplier multiplicand product 0initial0101 0000 0010 0000 0000 11.a0101 0000 00100000 0010 201010000 01000000 0010 300100000 01000000 0010 2200100000 10000000 0010 300010000 10000000 0010 31.a00010000 10000000 1010 200010001 00000000 1010 300000001 00000000 1010 4200000010 00000000 1010 300000010 00000000 1010 0010 x 0101 = 0000 1010

37. 37 Multiplier Algorithm Version 1 observations from version 1 1/2 bits in multiplicand always 0 use 64-bit adder is wasted (for 32 bit x 32 bit) 0’s inserted into multiplicand as shifted left, least significant bits of the product does not change once formed 3 steps per bit shift product to right instead of shifting multiplicand to left ? (by adding to the left half of the product register)

38. 38 Multiply Hardware Version 2 multiplicand 32 bits shift right 32-bit ALU multiplier product shift right control 32 bits 32-bit multiplicand reg. 32-bit ALU, 64-bit product reg. 32-bit multiplier reg ADD Check the right most bit of M’r to decide to add 0 or multiplicand Write into the left half of the product register write 32 bits

39. 39 Multiply Algorithm Version 2 1. test multiplier0 (i.e., bit 0 of the multiplier) 1a. if multiplier0 = 1 add multiplicand to the left half of product and place the result in the left half of product register; 2. shift product reg. right 1 bit 3. shift multiplier reg. right 1 bit 4. 32nd repetition ? if yes done if no, go to 1.

40. 40 Multiply Algorithm Version 2 Example iter. step multiplier multiplicand product 0initial001100100000 0000 11.a001100100010 0000 2001100100001 0000 3000100100001 0000 21.a000100100011 0000 2000100100001 1000 3000000100001 1000 32000000100000 1100 3000000100000 1100 42000000100000 0110 3000000100000 0110

41. 41 Multiply Version 2 Observations –product reg. wastes space that exactly matches the size of multiplier –3 steps per bit –combine multiplier register and product register

42. 42 Multiply Hardware Version 3 32-bit multiplicand register, 32-bit ALU, 64-bit product register, multiplier reg is part of product register multiplicand 32 bit ALU product (multiplier) control shift right write into left half ADD

43. 43 Multiply Algorithm Version 3 1. test product0 (multiplier is in the right half of product register) 1a. if product0 = 1 add multiplicand to the left half of product and place the result in the left half of product register 2. shift product register right 1 bit 3. 32nd repetition ? if yes, done if no, go to 1.

44. 44 Multiply Algorithm Version 3 Example iter. step multiplicand product 0initial11100000 1011 11.a11101110 1011 211100111 0101 21.a1110 10101 0101 211101010 1010 3211100101 0101 41.a1110 10011 0101 211101001 1010 1110 x 1011 1110 x 1011 = 1001 1010 14 x 11 = 154 need to save the carry

45. 45 Multiply Algorithm Version 3 Observations 2 steps per bit because of multiplier and product in one register, shift right 1 bit once (rather than twice in version 1 and version 2) MIPS registers Hi and Li correspond to left and right half of product MIPS has instruction multu How about signed numbers in multiplication ? –method 1: keep the sign of both numbers and use the magnitude for multiplication, after 32 repetitions, then change the product to appropriate sign. –method 2: Booth’s algorithm –Booth’s algorithm is more elegant in signed number multiplications –Booth’s algorithm uses the same hardware as version 3

46. 46 Booth’s Algorithm Motivation for Booth’s Algorithm is speed example 2 x 6 = 0010 x 0110 normal approach Booth’s approach 00100010 0110 0110 Booth’s approach : replace a string of 1s in multiplier by two actions action 1: beginning of a string of 1s, subtract multiplicand action 2: end of a string of 1s, add multiplicand

47. 47 Booth’s Algorithm end of run middle of run beginning of run 011111111111111111110 current bit bit to the right explanation action (previous bit) 1 0 beginning of a run of 1s sub. mult’d from left half of product 1 1 middle of a run no arithmetic oper. 0 1 end of a run add mul’d to left half of product 0 0 middle of a run of 0s no arith. operation.

48. 48 Booth’s Algorithm Example iteration step multiplicand product 0 initial11100000 01110 1 sub. 11100010 01110 product shift right 11100001 00111 2 shift right11100000 10011 3 shift right11100000 01001 4 add11101110 01001 shift right11101111 00100 -2 x 7=-14 in signed binary 1110 x 0111 = 1111 0010 previous bit To begin with we put multiplier at the right half of the product register

49. 49 Divide Algorithm Paper and pencil quotient divisor dividend remainder (modulo ) 10101010101011

50. 50 Divide Hardware Version 1 64-bit divisor reg., 64-bit ALU, 32-bit quotient reg. 64-bit remainder register divisor shift right 64-bit ALU remainder quotient control shift left write put the dividend in the remainder register initially

51. 51 Divide Algorithm Version 1 start: place dividend in remainder 1. sub. divisor from the remainder and place the result in remainder 2. test remainder 2a. if remainder >= 0, shift quotient to left setting the new rightmost bit to 1 2b. if remainder <0, restore the original value by adding divisor to remainder, and place the sum in remainder. shift quotient to left and setting new least significant bit 0 3. shift divisor right 1 bit 4. n+1 repetitions ? if yes, done, if no, go to 1.

52. 52 Divide Algorithm Version 1 Example iter. step quotient divisor remainder 0initial00000010 00000000 0111 1100000010 00001110 0111 2b00000010 00000000 0111 300000001 00000000 0111 2100000001 00001111 0111 2b00000001 00000000 0111 300000000 10000000 0111 3100000000 10001111 1111 2b00000000 10000000 0111 300000000 01000000 0111 4100000000 01000000 0011 2a00010000 01000000 0011 300010000 00100000 0011 5100010000 00100000 0001 2a00110000 00100000 0001 300110000 00010000 0001

53. 53 Divide Algorithm Version 1 Observations –1/2 bits in divisor always 0 –1/2 of divisor is wasted –1/2 of 64-bit ALU is wasted Possible improvement –instead of shifting divisor to right, shifting remainder to left ? –first step can not produce a 1 in quotient, so switch order to shift first and then subtract. This can save one iteration

54. 54 Divide Hardware Version 2 32-bit divisor reg. 32-bit ALU, 32-bit quotient reg., 64-bit remainder reg. divisor 32-bit ALU remainder control quotient shift left

55. 55 Divide Algorithm Version 2 start: place dividend in remainder 1. shift remainder left 1 bit 2. sub. divisor from the left half of remainder and place the result in the left half of remainder 3. test remainder 3a. if remainder >= 0, shift quotient to left setting the new rightmost bit to 1 3b. if remainder <0, restore the original value by adding divisor to the left half of remainder, and place the sum in the left of the remainder. also shift quotient to left and setting new least significant bit 0 4. n repetitions ? if yes, done, if no, go to 1.

56. 56 Divide Algorithm Version 2 Example iter. step quotient divisor remainder 0initial000000110000 1111 11000000110001 1110 2000000111110 1110 3b000000110001 1110 21000000110011 1100 2000000110000 1100 3a000100110000 1100 31000100110001 1000 2000100111110 1000 3b001000110001 1000 41001000110011 0000 2001000110000 0000 3a010100110000 0000

57. 57 Divide Algorithm Version 2 Observations –3 steps (shift remainder left, subtract, shift quotient left) Further improvement (version 3) –eliminating quotient register by combining with remainder register as shifted left –therefore loop contains only two steps, because the shift of remainder is shifting the remainder in the left half and the quotient in the right half at the same time –consequence of combining the two registers together is the remainder shifted one time unnecessary at the last iteration –final correction step: shift back the remainder in the left half of the remainder register (i.e., shift right 1 bit of remainder only)

58. 58 Divide Hardware Version 3 32-bit divisor register, 32-bit ALU, 64-bit remainder register, 0-bit quotient register (quotient bit shifts into remainder register, as remainder register shifts left) divisor 32-bit ALU remainder, quotient control 64-bit 32bits shift left write

59. 59 Divide Algorithm Version 3 start: place dividend in remainder 1. shift remainder left 1 bit 2. sub. divisor from the remainder and place the result in remainder 3. test remainder 3a. if remainder >= 0, shift remainder to left setting the new rightmost bit to 1 3b. if remainder <0, restore the original value by adding divisor to the left half of remainder, and place the sum in the left of the remainder. also shift remainder to left and setting new least significant bit 0 4. n repetitions ? if yes, done, if no, go to 2.

60. 60 Divide Algorithm Version 3 Example iter. step divisor remainder 0initial01010000 1110 101010001 1100 1201011100 1100 3b01010011 1000 2201011110 1000 3b01010111 0000 3201010010 0000 3a01010100 0001 4201011111 0001 3b01011000 0010 0100 0010 correction step: shift remainder right 1bit. quotient

61. 61 Divide Algorithm Version 3 Observations –same hardware as multiply, need a 32-bit ALU to add and subtract and a 64-bit register to shift left and right –divide algorithm version 3 is called restoring division algorithm for unsigned numbers Signed numbers divide –simplest method »remember signs of dividend and divisor, make positive, and finally complement quotient and remainder as necessary »dividend and remainder must have the same sign »quotient is negative if dividend sign and divisor sign disagree –SRT (named after three persons) method »an efficient algorithm

62. 62 Floating Point Numbers What can be represented in N bits ? unsigned 0 2 N -1 2’s complement. -2 N- 1 2 N-1 - 1 1’s comp.-2 N-1 + 1 2 N-1 - 1 BCD0 10 N/4 - 1 How about very small numbers, very large numbers rationals, such as 2/3; irrationals such as  2; transcendentals, such as , .

63. 63 Floating Point Numbers Mantissa (aka Significand), Exponent (using radix of 10) 6.12 x 10 23 IEEE standard F.P. mantissa = sign + magnitude; magnitude is normalized with hidden integer bit: 1.M exponent = E -127 (excess 127), 0 < E < 255 a FP number N = (-1) S 2 (E-127) (1.M) 0 = 0 00000000 00000000000000000000000 -1.5 = 1 01111111 10000000000000000000000 single precision S(1bit), E(8 bits), M(23 bits) S E M

64. 64 Floating Point Numbers Single Precision FP numbers - 0.75 = __________________________________ - 5.0 = ___________________________________ 7 = ____________________________________ -0.75 =-0.11 b =-1.1 x 2 -1 E=126 1 01111110 10000.......0 -5.0 = -101.0 b =-1.01 x 2 2 E=129 7 = 111 b = 1.11 x 2 2 E=129

65. 65 Floating Point Numbers Single precision FP number What is the smallest number in magnitude ? (1.0) 2 -126 What is the largest number in magnitude ? (1.11111111111111111111111) binary 2 127 = (2 - 2 -23 ) 2 127

66. 66 Floating Point Numbers single precision FP numbers ExponentSignificandObject represented 0 0 0 0 nonzero denormalized numbers 1 to 254 anything floating point numbers 255 0 infinite 255 nonzero NaN (Not A Number) other topics in FP numbers 1. extra bits for rounding 2. guard bit, sticky bit 3. algorithms for FP numbers

67. 67 Floating Point Numbers Double precision –64 bits total »52-bit significand »11-bit exponent (excess 1023 bias) –Number is: (-1) s (1.M) x 2 E-1023

68. 68 Basic Addition Algorithm Steps for Y + X, assuming Y >= X 1. Align binary points (denormalize smaller number) a. compute Diff = Exp(Y) - Exp(X); Exp = Exp(Y) b. Sig(X) = Sig(X) >> Diff 2. Add the aligned components Sig = Sig(X) + Sig(Y) 3. Normalize the sum 1. shift Sig right/left until leading bit is 1; decrementing or incrementing Exp. 2. Check for overflow in Exp 3. Round 4. repeat step 3 it not still normalized

69. 69 Addition Example 4-bit significand 1.0110 x 2 3 + 1.1000 x 2 2 align binary points (denormalize smaller number) 1. 0110 x 2 3 0. 1100 x 2 3 Add the aligned components 10. 0010 x 2 3 Normalize the sum 1.0001 x 2 4 No overflow, no rounding

70. 70 Another Addition Example 1.0001 x 2 3 - 1.1110 x 1 –4-bit significand; extra bit needed for accuracy 1. Align binary point: 1. 0001 x 2 3 - 0. 01111 x 2 3 2. Subtract the aligned components 0. 10011 x 2 3 3. Normalize 1.0011 x 2 2 = 4.75 Without extra bit, the result would be 0.1001 x 2 3 = 100.1 = 4.5, which is off by 0.25. This is too much!

71. 71 Accuracy and Rounding Want arithmetic to be fully precise –IEEE 754 keeps two extra digits on the right during intermediate calculations (guard digit, round digit) Alignment step can cause data to be discarded (shifted out on right) 2.56 x 10 0 + 2.34 x 10 2 2.3400 x 10 2 + 0.0256 x 10 2 2.3656 x 10 2 (We have two digits to round 0 to 49 round down Guard Round Answer = 2.37 x 10 2 Without using Guard and Round digits, Answer would be 2.36 x 10 2 51 to 99 round up