2. Princess Sumaya Univ. Computer Engineering Dept. Chapter 3:

3. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 1 / 42 Signed Number Representations  Sign-Magnitude Example: + 5 = – 5 = Range:  2’s Complement Example: + 5 = – 5 = S Magnitude –7 ≤ N ≤ +7–(2 n –1 –1) ≤ N ≤ +(2 n –1 –1) 0 Magnitude 1 2’s Complement

4. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 2 / 42 Signed Number Representations  2’s Complement Range: Exercise: Calculate the range for 8 bits –(2 n –1 ) ≤ N ≤ +(2 n –1 –1) 8 Combinations

5. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 3 / 42  Used to represent integers, both positive & negative  Distinguish: “2’s Comp. System” from “2’s Comp. Operation” Example: Represent the number +5 in 2’s Comp. System Correct:Incorrect: +5 = ( ) 2 ( ) 2 2’s Complement System

6. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 4 / 42 2’s Complement System Example: Given a number represented in 2’s comp. system, write an algorithm to square it. Answer 1) 2) 3)

7. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 5 / 42  Bit-by-bit addition, with carry propagation.  Unsigned Binary Operands: ●Produces unsigned binary ●Possible overflow (Cy = 1)  Signed 2’s Comp. Operands: ●Produces 2’s complement ●Possible overflow C y  C y-1 +. Addition +. +.

8. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 6 / 42 –. . +. Subtraction  2’s Complement Addition  Unsigned Binary Operands: ●If Cy = 1, result is unsigned binary ●If Cy = 0, result is negative (2’s comp) ●No overflow  Signed 2’s Comp. Operands: ●Produces 2’s complement ●Possible overflow C y  C y-1 –. . +.

9. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 7 / 42 ×. +. +.. +... Multiplication  Bit-by-bit Multiplication  Unsigned Binary Operands ●Unsigned result ●2n-bit result from n × n bits operands ●No overflow ●Partial Sum 0 1 1 0 × 0 1 0 1 0 1 1 0 0 0 0 0. 0 1 1 0.. 0 0 0 0... Partial Sum 0 0 0 0 + =

10. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 8 / 42 Sequential Multiplication 0 0 0 0 1 1 1 1 0 0 0 0 Multiplicand Product Multiplier 0 1 1 1 × 0 1 0 1 1 1 0 0 0 0. 0 1 1 0.. 0 0 0 0... Control Unit ALU

11. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 9 / 42 Sequential Multiplication 0 0 0 0 1 1 1 1 0 0 0 0 Multiplicand Product Multiplier Control Unit 0 1 Add Load 1 1 1 × 0 1 0 1 1 1 0 0 0 0. 1 1 1 1.. 0 0 0 0... ALU

12. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 10 / 42 Sequential Multiplication 0 0 0 0 1 1 1 1 Multiplicand Product Multiplier 0 1 Control Unit Shift Left Shift Right 1 1 × 0 1 0 1 1 1 0 0 0 0. 1 1 1 1.. 0 0 0 0... ALU

13. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 11 / 42 Sequential Multiplication 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 Multiplicand Product Multiplier 1 1 × 0 1 0 1 1 1 0 0 0 0. 1 1 1 1.. 0 0 0 0... 0 Shift Left Shift Right 0 0 1 0 Control Unit ALU

14. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 12 / 42 Sequential Multiplication 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 Multiplicand Product Multiplier 1 1 × 0 1 0 1 1 1 0 0 0 0. 1 1 1 1.. 0 0 0 0... Add Load 1 0 0 0 1 Shift Left Shift Right Control Unit ALU

15. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 13 / 42 Sequential Multiplication 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1 1 Multiplicand Product Multiplier 1 1 × 0 1 0 1 1 1 0 0 0 0. 1 1 1 1.. 0 0 0 0... 0 0 0 Shift Left Shift Right Control Unit ALU

16. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 14 / 42 Sequential Multiplication 1 1 1 1 0 0 0 0 0 1 0 0 1 0 1 1 Multiplicand Product Multiplier 1 1 × 0 1 0 1 1 1 0 0 0 0. 1 1 1 1.. 0 0 0 0... 1 0 0 1 0 1 1 0 0 0 00 0 0 0 Control Unit  Delay: Number of Clocks =.... Clocks ALU

17. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 15 / 42 Sequential Multiplication 0 0 0 0 M M M M 0 0 0 0 Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit m m ALU Clock

18. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 16 / 42 Sequential Multiplication 0 0 0 M M M M 0 0 0 0 0 p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit 0 m m m ALU Clock

19. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 17 / 42 Sequential Multiplication 0 0 M M M M 0 0 0 0 p p p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit 0 0 m m ALU Clock

20. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 18 / 42 Sequential Multiplication 0 M M M M 0 0 0 0 p p p p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit 0 0 0 m ALU Clock

21. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 19 / 42 Sequential Multiplication M M M M 0 0 0 0 p p p p Multiplicand Product Multiplier  Delay: Number of Clocks =.... Clocks Control Unit 0 0 0 00 0 0 0 ALU Clock

22. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 20 / 42 Multiplication  ALU Size? 0 1 1 0 × 0 1 0 1 Partial Sum Partial Sum: 0 0 0 0 + 0 1 1 0 Partial Sum Partial Sum: 0 0 1 1 0 + 0 0 0 0 Partial Sum Partial Sum: 0 0 1 1 0 + 0 1 1 0 Partial Sum Partial Sum: 0 0 1 1 1 1 0 0 0 0 0 1 1 0

23. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 21 / 42 Signed Multiplication  Signed 2’s Comp. Operands: ●Convert negative operands to positive values ●Perform unsigned multiplication ●Negate the result if the two operands differ in sign

24. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 22 / 42 Division  Subtract Divisor & Drop a Bit  Unsigned Binary Operands ●Unsigned result ●2n-bit Dividend by n-bit divisor  n-bit quotient and n-bit remainder ●Possible overflow (big quotient) ♦ Divide by zero ♦ Quotient ≥ 2 n.. │ 0 0

25. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 23 / 42 Sequential Division 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 Divisor Remainder (Dividend) Quotient 0 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0

26. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 24 / 42 Sequential Division 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 Divisor Remainder (Dividend) Quotient 0 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Subtract Load

27. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 25 / 42 Sequential Division 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 Divisor Remainder Quotient 0 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Add Load Shift Left 0 Shift Right

28. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 26 / 42 Sequential Division 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 Divisor Remainder Quotient 0 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Subtract Load

29. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 27 / 42 Sequential Division 0 0 1 1 0 0 0 0 0 0 1 0 Divisor Remainder Quotient 0 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Shift Left 1 Shift Right

30. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 28 / 42 Sequential Division 0 0 0 1 1 0 0 0 0 0 1 0 Divisor Remainder Quotient 0 0 0 1 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Subtract Load

31. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 29 / 42 Sequential Division 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 Divisor Remainder Quotient 0 0 0 1 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Shift Left 1 Shift Right

32. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 30 / 42 Sequential Division 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 Divisor Remainder Quotient 0 0 1 1 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Subtract Load

33. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 31 / 42 Sequential Division 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 0 Divisor Remainder Quotient 0 0 1 1 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 0 1 0 1 0 – 0 1 1 0 0 1 0 0 Add Load Shift Left 0 Shift Right

34. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 32 / 42 Sequential Division 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 Divisor Remainder Quotient 0 1 1 00 1 1 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 – 0 1 1 0 0 1 0 0 Subtract Load

35. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 33 / 42 Sequential Division 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 Divisor Remainder Quotient 0 1 1 00 1 1 0 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 – 0 1 1 0 0 1 0 0 Shift Left 1 Shift Right

36. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 34 / 42 Sequential Division 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 Divisor Remainder Quotient 1 1 0 11 1 0 1 Control Unit ALU. 0 1 1 0 1 0 1 1 0│0 1 0 1 0 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 1 0 0 – 0 1 1 0 0 0 1 0 0 0 0 – 0 1 1 0 0 0 0 1 0 1 0 – 0 1 1 0 0 + 0 1 1 0 0 1 0 – 0 1 1 0 0 1 0 0 How many times was the Divisor & Quotient shifted? How many clocks?

37. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 35 / 42 Signed Division  Signed 2’s Comp. Operands: ●Convert negative operands to positive values ●Perform unsigned division ●Negate the result (?) if the two operands differ in sign ♦ Which result? Quotient or remainder or both? ●Dividend = Quotient × Divisor + Remainder ♦ Example: 16 ÷ 3 ●Rule: Dividend & Remainder must have the same sign

38. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 36 / 42 Floating Point  Scientific Notation Example: (10.5 × 10 – 7 is not good)  Normalized Scientific Notation Example: (0.105 × 10 – 5 is not good)  Binary Numbers Example: (0.0101 × 2 – 5 is not good) (Normalized). × 10. × 2

39. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 37 / 42 Floating Point  Sign & Magnitude  Overflow: The exponent is too large to be represented  Underflow: The exponent is too small to be represented  Single & Double Precision. × 2± S Exponent Fraction 32 bits ± ?

40. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 38 / 42 IEEE 754 Floating Point Standard  Single Precision:  Biased Exponent S Exponent Fraction 32 bits 1 bit 8 bits 23 bits 255 0 256 = 0111 1111 (biased by 127) 0 + –

41. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 39 / 42 IEEE 754 Floating Point Standard  Implicit ‘1’ 1.01 × 2 0 Examples: 75 = – 0.75 = 0.0 = ? S Exponent Fraction This bit is always 1 No need to store it, hence implicit ( ) 2 0 1000 0101 0 0 1 0 1 1 0 0 – ( ) 2 1 0111 1110 1 0 0 0 0

42. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 40 / 42 IEEE 754 Floating Point Standard  Reserved Bit Patterns ●Zero: ●± Infinity: ●Others like denormalized number and Not-a-Number 0 0000 0000 0 0 0 0 0 1111 1111 0 0 0 0 0

43. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 41 / 42 Floating-Point Addition / Subtraction  Need to Align Decimal Points Example: Add 0.5 + 0.4375 Normalized Forms: Align Decimal Point: Perform Addition: Normalize Result: 0.5 = ( ) 2 = 0.4375 = ( ) 2 = 0 × 2 –1 0 0111 1110 0 0 0 0 0 0111 1101 1 1 0 0 0 0111 1110 1. 0 0 0 0 0 0111 1101 1. 1 1 0 0 0 0111 1110 0. 1 1 1 0 0 0111 1110 1. 1 1 1 0 0 0111 1110 1 1 1 0

44. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 42 / 42 Floating-Point Multiplication  Need to Account for Biased Exponents Example: Multiply 0.5 × 0.4375 Normalized Forms: Multiply Fractions: Add Exponents: Sub Extra Bias: Round & Normalize: 0.5 = ( ) 2 = 0.4375 = ( ) 2 = 0 0111 1110 0 0 0 0 0 0111 1101 1 1 0 0 ×. 0 0111 1110 1. 0 0 0 0 0 0111 1101 1. 1 1 0 0 + –. 0 0111 1100 1 1 0 0

45. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. Chapter 3

46. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. Chapter 3 Exercise 1  Determine the magnitude of (10001000) 2 in: a) sign-magnitude and b) 2’s complement system  Determine if there was an overflow error in: unsigned int a, b; // Assume 8-bit registers a= (10001000) 2 ; b = a + a;  Show how the CPU computes b: int a, b; // Assume 8-bit registers a= (10001000) 2 ; b = a – a;  How many addition are done in (1001) 2.