1. CSET 4650 Field Programmable Logic Devices
Introduction to PLAs
Programmable Logic Arrays
CSET Field Programmable Logic Devices
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2. Programmable Logic Array (PLA)
Introduced in 1975
Predates the invention of the PAL
The first PLD
The most user-configurable of the traditional two-level programmable logic devices

3. Programmable Logic Array (PLA)
A PLA is a large 2-level AND / OR array with lots of inputs and product terms
Most general/flexible device of this architecture
PROM, PAL, PLA
Programmable connections for both AND / OR
Uses the sum of products (SOP) form

4. PLA Block Diagram
Same 2-level AND/OR logic arrangement as with PROM and PAL devices
programmable
shareable

5. PLA Description the third simple PLD we will study
decode only some of the input addresses (PROMs decoded all of them)
increased propagation delay because of both the AND and OR array inputs are programmable
naming convention not as systematic as PALs
also called FPLAs

6. PLA: A More General Idea
A PAL has limits on the arrangement of its sum-of-products groupings.
Programmed Array Logic
A PLA has complete flexibility of its sum-of-products groupings.
Programmable Logic Array

7. Programmable Logic Array (PLA)
n input variables
AND gates have 2n inputs
true and inverted form of each input variable
m outputs
driven by large OR gates
each AND gate is programmably connected to each output’s OR gate (shareable product terms)

8. Nomenclature: 4x6x3 PLA

9. Compact Representation
Illustration of a 4-input, 6 product term, 3-output PLA
4x6x3
All fuses shown intact (not yet programmed)
This representation is closer to the “wired logic” physical implementation

10. PLA Electrical Design
fuse detail
Wired Logic
fuse detail

11. PLA: Sharing Product TermsB A C D F G H J
ABC
ABC AD
F = ABC + AD + AD
G = ABC + ABC + AD
H = ABC + BD
J = B + AD AD BD B

12. Sharing Product Terms P1 P2 P3 P4 P5 P6

13. Example: Programming a PLA
Given:
F1 = Σm(2, 4, 5, 7)
F2 = Σm(0, 1, 2, 4, 6)
Use K-maps to minimize and look for common product terms
Program functions into a simple PLA
minterm form

14. F1 K-Map Minimization B BC ABC A C AC AB
Three-variable K-map for F1 = Σm(2, 4, 5, 7) C B A 1 3 2 4 5 7 6 BC
ABC F1 AB AC

15. F2 K-Map Minimization B BC BC A C AC
Three-variable K-map for F2 = Σm(0, 1, 2, 4, 6) C B A 1 3 2 4 5 7 6 BC BC F2 AC

16. Programming the PLA
Product Terms AB AC BC
ABC

17. XOR: Like a programmable inverter …
Programming
XOR: Like a programmable inverter …
Tied to 0 – F1 not inverted
Tied to 1 – F1 is inverted

18. PLA Example 2 Functions to implement are: = ABC + ABC + ABC + ABC
standard form

19. Group both 1s and 0s to find fewest product terms
Minimum Product Terms
Fewest are
Group both 1s and 0s to find fewest product terms

20. PLA Programming Table Indicates intact fuse locations
true or complemented
Indicates intact fuse locations
Helps to identify shared terms

21. PLA For Example 2 3 inputs 4 product terms 2 outputs
optional inversion of outputs

22. Circuit For Example 2
Note the inversion of the output to generate F1

23. Before Programming Express functions in SOP form
Try to reduce the number of product terms
To use fewer of the rows
Look at both 1s and 0s
Number of literals in each term not as important
Fewer may make circuit faster

24. Create Programming Table
What really gets generated is the programming table
Chip programmed in special-purpose programming device
uses personality modules for different devices

25. PROM, PAL, PLA Assignment
Sandige, Chapter 7
7 – 39
7 – 42
7 – 44
7 – 48
Write out on paper & photocopies from book
Due on Wednesday, September 8, 2004 at start of class