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Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 – Selected Design Topics Part 4 – Programmable.

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Presentation on theme: "Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 – Selected Design Topics Part 4 – Programmable."— Presentation transcript:

1 Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 – Selected Design Topics Part 4 – Programmable Implementation Technologies Logic and Computer Design Fundamentals

2 Chapter 6 - Part 4 2 Overview  Programmable Implementation Technologies (section 6.8) Why Programmable Logic? Read-Only Memories (ROMs) Programmable Logic Arrays (PLAs) Programmable Array Logic (PALs)

3 Chapter 6 - Part 4 3 Why Programmable Logic?  Small and Medium Scale Integration Up to 200 gates per device/IC Most common is 74xx series (gates, FF, Decoders …)  Advantages Easy to understand functions Exceptional Signal Visibility  Disadvantages Low logic density means big boards or small designs Higher power consumption Failure concern per function

4 Chapter 6 - Part 4 4 Why Programmable Logic?  Large Scale Integration Ranging from 200 to 200,000 gates per device. Small memories, programmable logic devices  Advantages Higher logic density means smaller boards or larger designs. Many devices can be programmed and reprogrammed, saving expense when changes are made.  Disadvantages Need to learn how to use and program Signal visibility is reduced

5 Chapter 6 - Part 4 5 Why Programmable Logic ?  Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environment  Most programmable logic devices are erasable and reprogrammable. Allows “updating” a device or correction of errors Allows reuse the device for a different design - the ultimate in re-usability! Ideal for course laboratories

6 Chapter 6 - Part 4 6 Programmable Configurations  Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates  Programmable Array Logic (PAL) - a programmable array of AND gates feeding a fixed array of OR gates.  Programmable Logic Array (PLA)  - a programmable array of AND gates feeding a programmable array of OR gates. PAL is a registered trademark of Lattice Semiconductor Corp.

7 7 Gate Symbols Figure 6-18 Conventional and Array Logic Symbols for OR Gate

8 Chapter 6 - Part 4 8 Read Only Memory  Read Only Memories (ROM) or Programmable Read Only Memories (PROM) are OP logic devices with a fixed AND array and a programmable OR array.  have: k input lines, m output lines, and m = 2 k decoded minterms n OR gates  Usually referred as 2 k x n ROM  Can implement n functions with k inputs k-to-2 k line decoder D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1F2 F3 X X X X X X X X X X

9 Chapter 6 - Part 4 9 Read Only Memory  A program for a ROM or PROM is simply a multiple- output truth table If a 1 entry, a connection is made to the corresponding minterm for the corresponding output If a 0, no connection is made  There is no advantage of simplifying the function when using ROM since we need to specify the entire list of minterms.  Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names!

10  Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)  The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms.  The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the OR  Read Example: For input (A 2,A 1,A 0 ) = 001, output is (F 3,F 2,F 1,F 0 ) =  What are the simplified expressions for F 3, F 2, F 1 and F 0 in terms of (A 2, A 1, A 0 )? Chapter 6 - Part 4 10 Read Only Memory Example D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1F2 F3 X X X X X X X X X X

11 Chapter 6 - Part 4 11 P rogrammable Array Logic (PAL )  PAL is the opposite of ROM; it is PLD that has a programmable AND array and a fixed OR array.  Function has to be reduced into SOP before it is programmed into the PAL  Disadvantage ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates.  Advantages For given internal complexity, a PAL can have larger k (inputs) and n (outputs) Some PALs have outputs that can be complemented, adding POS functions

12 12 Figure

13 Chapter 6 - Part 4 13 P rogrammable Logic Array (PLA )  Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.  A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL OR gates  Some PLAs have outputs that can be complemented (using XOR gates), adding POS functions

14 Chapter 6 - Part 4 14 Programmable Array Logic (PLA)  The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. Fuse intact Fuse blown 1 F 1 F 2 X A B C CCBBAA X X X X X X X X X X X X X X A B A C B C A B X 3-input, 3-output PLA with 4 product terms Used to produce POS or complement of function

15 Chapter 6 - Part 4 15 ROM, PAL and PLA Summary (a) Programmable read-only memory (PROM) Inputs Fixed AND array (decoder) Programmable OR array Outputs Programmable Connections (b) Programmable array logic (PAL) device Inputs Programmable AND array Fixed OR array Outputs Programmable Connections (c) Programmable logic array (PLA) device Inputs Programmable OR array Outputs Programmable Connections Programmable Connections Programmable AND array


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