1. Binary Operations I0.0 I0.1 Q 8.0 Q 8.1 I 1.0 ( MCR< ) (MCRA) Q 8.0
( ) SR S Q R
I1.2
I1.3
M0.0
Q 9.3
Contents Page
Cyclical Program Execution …
Process Images
Program Structure
Types of Program Blocks
Normally Open and Normally Closed Contacts. Sensors and Symbols
Exercise
Addressing of S7-300 Modules ………
DI/DO Addressing in Multi-Tier Configurations
Binary Logic Operations: AND, OR
Binary Logic Operations: Exclusive OR (XOR)
Result of Logic Operation, First Check. Examples…
Assignment, Setting, Resetting
Setting / Resetting a Flip Flop
Connector
Instructions that Affect the RLO …………
Master Control Relay Function
Unconditional Jump (Independent of RLO)
Conditional Jump (Dependent on RLO)
RLO Edge Detection …
Signal Edge Detection …
Exercise: Program for a Bottling Plant (Mode Selection) …………

2. Cyclical Program Execution
Start-up block (OB 100)
Execution once after e.g. power on
Start of the cycle monitoring time
Input
Module
CPU Cycle
Reading the signal states from the modules
and saving the data in the process image (PII)
Execution of the program in OB1
(cyclical execution)
Events (time-of-day interrupt, hardware interrupts etc.)
call other OBs, FBs, FCs, etc.
A I 0.1
A I 0.2
= Q8.0
Block
OB 1
Output
Module
Starting The CPU carries out a complete restart (with OB100) when switching on or when switching from STOP --> RUN. During a complete restart, the operating system deletes the non-retentive bit memories, timers and counters, deletes the interrupt stack and block stack, resets all stored hardware interrupts and diagnostic interrupts and starts the scan cycle monitoring time.
Scan Cycle The cyclical operation of the CPU consists of three main sections, as shown in the diagram above:
• The CPU checks the status of the input signals and updates the process- image input table.
• It executes the user program with the respective instructions.
• It writes the values from the process-image output table into the output modules.
Writing the process-image output table
(PIQ) to the output modules

3. Process Images PII PIQ User Program Byte 0 Byte 1 Byte 2 :
CPU Memory Area
Byte 0
Byte 1
Byte 2 : 1 :
A I 2.0 1
Introduction The CPU checks the status of the inputs and outputs in every cycle. There are specific memory areas in which the module‘s binary data are stored: PII and PIQ. The program accesses these registers during processing.
PII The process-image input table is found in the CPU‘s memory area. The signal state of all inputs is stored there.
PIQ The process-image output table contains the output values that result from the program execution. These are sent to the actual outputs (Q) at the end of the cycle.
User Program When you check inputs in the user program with, for example, A I 2.0, the last state from the PII is evaluated. This guarantees that the same signal state is always delivered when there is multiple checking of the input within one cycle.
= Q 4.3 :
CPU Memory Area

4. Program Partitioned into Areas
Program Structure
Linear Program
Program Partitioned into Areas
Structured Program
All instructions are found in one block (normally in the organization block OB 1)
The instructions for the indi- vidual functions are found in individual blocks. OB 1 calls the individual blocks one after the other.
Reuseable functions are loaded
into individual blocks. OB 1 (or other blocks) call these blocks and pass on the
pertinent data.
OB 1
Recipe A
Recipe B
Mixer
Outlet
OB 1
Pump
Outlet
OB 1
Linear Program The entire program is found in one continuous program block.
This model resembles a hard-wired relay control, that was replaced by a programmable logic controller. The CPU processes the individual instructions one after the other.
Partitioned The program is divided into blocks, whereby every block only contains the
Program program for solving a partial task. Further partitioning through networks is possible within a block. You can generate network templates for networks of the same type.
The organization block OB 1 contains instructions that call the other blocks in a defined sequence.
Structured A structured program contains blocks with parameters, so-called parameter
Program assignable blocks. These blocks are designed in such a way that they can be used universally.
When a parameter assignable block is called, it is given current parameters (the exact addresses of inputs and outputs as well as parameter values).
Example:
• A "pump block" contains instructions for the control of a pump.
• The program blocks, that are responsible for the control of special pumps, call the "pump block" and give it information about which pump is to be controlled with which parameters.
• When the "pump block" has completed the execution of its instructions, the program returns to the calling block (e.g. OB 1), which continues with the processing of its instructions.

5. Types of Program Blocks
Operating System
Cycle OB
Organization
Blocks FB
SFB FC
Time
Process FB FB
SFC
Error
User Blocks User blocks contain the program code and the user program data.
In a structured user program, some blocks are called and processed cyclically, others only as required.
System Blocks System blocks are pre-defined functions or function blocks that are integrated in the CPU‘s operating system. These blocks do not occupy additional space in the user memory.
System blocks are called from the user program. These blocks have the same interface, the same identifier and the same number throughout the entire system. The user program is thus easily transportable between various CPUs or programmable controllers.
OB = Organization Block
FB = Function Block
FC = Function
SFB = System Function Block
SFC = System Function
FB with instance
data block
Legend:

6. Normally Open and Normally Closed Contacts, Sensors and Symbols
Interpretation in PLC program
Process
activated
not
The sensor
is ...
Voltage
present at
input?
Signal
state at
input
Check for
signal state “1”
Check for
signal state “0”
The sensor
is a ...
Symbol /
Instruction
Result of
check
Symbol /
Instruction
Result of
check
Yes 1
“Yes“ 1
“No”
NO contact
LAD:
“NO contact”
LAD:
“NC contact” No
“No”
“Yes” 1
&
FBD:
&
FBD:
NC contact
activated No
“No”
“Yes” 1
Process The use of normally open or normally closed contacts for the sensors in a controlled process depends on the safety regulations for the process.
Normally closed contacts are always used for limit switches and safety switches, so that dangerous conditions do not arise if a wire break occurs in the sensor circuit.
Normally closed contacts are also used for switching off machinery for the same reason.
Symbols In LAD, a symbol with the name "NO contact" is used for checking for signal state "1" and a symbol with the name "NC contact" to check for signal state "0". It makes no difference whether the process signal “1” is supplied by an activated NO contact or a non-activated NC contact.
Example The result of check for the "NO contact" symbol is "1" if an NC contact in the machine is not activated.
not
activated
Yes 1
“Yes” 1
“No”
A I x.y
STL:
AN I x.y
STL:

7. Exercise
Task: In all three examples the light should be on when S1 is activated and S2 is not activated!
Hardware
I1.0 S1
I1.1 S2
I1.0 S1
I1.1 S2
I1.0 S1
I1.1 S2
I 1.0
I 1.1
Q 4.0
Programmable controller
I 1.0
I 1.1
Q 4.0
Programmable controller
I 1.0
I 1.1
Q 4.0
Programmable controller
Light
Light
Light
Software
I 1.0
I 1.1
Q 4.0
I1.0
I1.1
Q 4.0
I1.0
I1.1
Q 4.0
LAD
Q 4.0
I 1.0
I1.1
&
Q 4.0
I1.0
I1.1
&
Q 4.0
I1.0
I1.1
&
FDB
Exercise Complete the programs above to obtain the following functionality: When switch S1 is activated and switch S2 is not activated, the light should be ON in all three cases.
Note ! The terms "NO contact" and "NC contact" have different meanings depending on whether they are used in the process hardware context or as symbols in the software.
I1.0
I1.1
Q 4.0
I1.0
I1.1
Q 4.0
I1.0
I1.1
Q 4.0
STL

8. Addressing of S7-300 Modules
Slot No.
PS CPU SM SM SM SM SM SM SM
Modules
Address 0.0
Address 0.7
Address 1.0
Address 1.7
Slot Numbers The slot numbers in the rack of an S7-300 simplify addressing within the S7-300 environment. The first address on a module is determined by the position of the module in the rack.
Slot 1 Power supply. This is the first slot by default.
A power supply module is not absolutely essential. An S7-300 can also be supplied with 24V direct.
Slot 2 Slot for the CPU.
Slot 3 Logically reserved for an interface module (IM) for multi-tier configurations using expansion racks. Even if no IM is installed, it must be included for addressing purposes.
You can physically reserve the slot (e.g. for installation of an IM at a later date) by inserting a DM370 dummy module.
Slots 4-11 Slot 4 is the first slot that can be used for I/O modules, communications processors (CP) or function modules (FM).
Addressing examples:
• A DI module in slot 4 begins with the byte address 0 .
• The top LED of a DO module in slot 6 is called Q8.0 .
Note 4 byte addresses are reserved for each slot. When using 16-channel DI/DO modules, two byte addresses are lost in every slot!

9. DI/DO Addressing in Multi-Tier Configurations
Rack 3
96.0 to
99.7
100.0
103.7
104.0
107.7
108.0
111.7
112.0
115.7
116.0
119.7
120.0
123.7
124.0
127.7 IM
(Receive) PS
Rack 2
64.0 to
67.7
68.0
70.7
72.0
75.7
76.0
79.7
80.0
83.7
84.0
87.7
88.0
91.7
92.0
95.7 IM
(Receive) PS
Rack 1 IM
(Receive)
32.0 to
35.7
36.0
39.7
44.0
47.7
48.0
51.7
52.0
55.7
56.0
59.7
60.0
63.7
40.0
43.7 PS
Multi-Tier The slots also have fixed addresses in a multi-tier configuration.
Configurations
Examples:
• Q7.7 is the last bit of a 32-channel DO module plugged into slot 5 of rack 0.
• IB105 is the second byte of a DI module in slot 6 of rack 3.
• QW60 is the first 2 bytes of a DO module in slot 11 of rack 1.
• ID80 is all 4 bytes of a 32-channel DI module in slot 8 in rack 2. PS
CPU IM
(Send)
0.0 to
3.7
4.0 to
7.7
8.0 to
11.7
12.0 to
15.7
16.0 to
19.7
20.0 to
23.7
24.0 to
27.7
28.0 to
31.7
Rack
Slot

10. Binary Logic Operations: AND, OR
(Q 8.0)
S1 (I 0.0)
S2 (I 0.1) L2
(Q 8.1)
Circuit Diag.
I0.0
I0.1
Q 8.0
Q 8.1
LAD =
Q 8.0
&
I 0.0
I 0.1
Q 8.1
FBD
A I0.0
A I0.1
= Q 8.0
= Q 8.1
STL
AND
L3 (Q 8.2) S3
(I 0.2) S4
(I 0.3)
I0.2
I0.3
Q 8.2
I 0.2
I 0.3
>=1 =
Q 8.2
O I0.2
O I0.3
= Q 8.2
Logic Tables
AND I 0.0 I 0.1 Q 8.0
OR I 0.2 I 0.3 Q 8.2
0 0
0 1
1 0
1 1 OR

11. Binary Logic Operations: Exclusive OR (XOR)
Q 8.0
LAD
>=1 =
Q 8.0
&
I 0.4
I 0.5
FBD
STL
A I0.4
AN I0.5 O
AN I0.4
A I0.5
= Q8.0
I 0.4
I 0.5
XOR =
Q 8.0
X I0.4
X I0.5
= Q8.0
Logic Table
XOR I 0.4 I 0.5 Q 8.0
0 0
0 1
1 0
1 1
Rule The following rule is valid for the logic operation of two addresses after XOR: the output has signal state "1", when one and only one of the two checks is fulfilled ("one and only one of two" ).
Attention! This rule cannot be generalized to "one and only one of n" ! for the logic operation of several addresses after XOR !!
As of the third XOR instruction, the old RLO is gated with the new result of check after XOR.

12. Result of Logic Operation, First Check. Examples
Signal State
Result of Check
Result of Logic
Operation
First Check 1
Example 2
Signal State
Result of Check
Result of Logic
Operation
First Check 1
Example 3
Signal State
Result of Check
Result of Logic
Operation
First Check
A I 1.0
AN I 1.1
A M 4.0
= Q 8.0
= Q 8.1
A I 2.0
Signal State A logic operation is made up of a series of instructions to check the states of signals (inputs (I), outputs (Q), bit memories (M), timers (T), counters (C) or data bits (D) ) and instructions to set Q,M,T,C or D.
Result of Check When the program is executed, the result of check is obtained. If the check condition is fulfilled, the result of check is “1”. If it is not fulfilled, the result of check is “0”.
First Check The result of the first check is stored as the result of logic operation (RLO).
Result of Logic When the next check instructions are executed, the result of logic operation is
Operation gated with the result of check and a new RLO is obtained.
When the last check instruction in a logic operation has been executed, the RLO remains the same. A number of instructions using the same RLO can follow.
Note The result of the first check is stored without being subjected to a logic operation. It therefore makes no difference whether you program the first check with an AND or an OR instruction in STL. To enable your program to be converted into one of the other programming languages, you should, however, always program using the correct instruction.

13. Assignment, Setting, Resetting
LAD
FBD
STL
( )
Q 8.0
I 1.0
I 1.1
& =
A I 1.0 A I 1.1 = Q 8.0
Assignment
(S)
Q 8.1
I 1.2
I 1.3
& S
A I 1.2 A I 1.3 S Q 8.1
Set
(R)
Q 8.1
I 1.4
>=1 R
I 1.5
O I 1.4 O I 1.5 R Q 8.1
Reset
Assignment An assignment passes the RLO on to the specified address (Q, M, D). When the RLO changes, the signal state of that address also changes.
Set If RLO= "1", the specified address is set to signal state "1" and remains set until it is reset by another instruction.
Reset If RLO= "1", the specified address is reset to signal state "0" and remains in this state until it is set again by another instruction.

14. Setting / Resetting a Flip Flop
LAD
FBD
STL SR R Q S
I1.2
I1.3
M0.0 =
Q9.3
Dominant
Reset
Q 9.3
A I 1.2 S M 0.0 A I 1.3 R M 0.0 A M 0.0 = Q 9.3 RS S Q R
I1.3
I1.2
M0.0 =
Q9.3
Dominant
Set
Q 9.3
A I 1.3 R M 0.0 A I 1.2 S M 0.0 A M 0.0 = Q 9.3
Flip Flop A flip flop has a Set input and a Reset input. The memory bit is set or reset, depending on which input has an RLO=1.
If there is an RLO=1 at both inputs at the same time, the priority must be determined.
Priority In LAD and FBD there are different symbols for Dominant Set and Dominant Reset functions. In STL, the instruction that was programmed last has priority.
Note If an output is set with a Set instruction, it is reset on a complete restart of the CPU.
If M 0.0 in the example above has been declared retentive, it will remain in the set state after a complete restart of the CPU and the reset output Q 9.3 will be be assigned the set state again.

15. Connector ( ) STL LAD A I 1.0 A I 1.1 = M 0.0 A M 0.0 A I 2.0 A I 2.1
NOT
= M 1.1
A M 1.1
= Q 4.0
STL
LAD
I 1.0
I 1.1
( )
M0.0
I 2.0
I 2.1
M 1.1
NOT
Q 4.0
I 1.0
I 1.1
&
I 2.0
I 2.1
M0.0
M1.1
Q 4.0 =
FBD
Connector A connector is an intermediate assignment element that stores the current RLO at a specified address.
When connected in series with other elements, the "Connector" instruction is inserted in the same way as a contact.
A connector must never:
• be connected to a power rail
• directly follow a branch
• be used at the end of a branch.
You can program a negated connector with the "NOT" element.

16. Instructions, that Affect the RLO
LAD
FBD
STL
A I0.0 A I0.1 NOT = Q8.0 =
Q8.0
&
I0.0
I0.1
( )
NOT
not available
CLR
not available
SET
I1.6
( SAVE )
SAVE
&
A I1.6 =
Q8.1 BR
( )
A BR
= Q 8.1
NOT The NOT instruction inverts the RLO.
CLR The CLEAR instruction changes the RLO to "0" (only available in STL at present!).
SET The SET instruction changes the RLO to "1" (only available in STL at present!).
SAVE The SAVE instruction saves the RLO as "BR" in a register (status word).
BR The statement “A BR" can be used to recheck the saved RLO.
Status word 15 8 1 BR
RLO

17. Master Control Relay Function
LAD
( MCRA )
I0.7
( )
Q8.5
M0.6
I0.4
( S )
Q16.0
M69.0
I4.7
M5.5
( MCR< )
( MCRD )
( MCR> )
I0.0
MCR<
&
A0.0
MCRA S
A0.4
Q16.0
MCR> =
M5.5
M69.0
I4.7
MCRD
A0.7
Q8.5
M0.6
FBD
MCRA // Activated
A I0.0 // Enable MCR
MCR( // Open MCR
A I0.7 // NO Contact
= Q8.5 // Output Coil
= M0.6 // Output Coil
A I0.4 // NO Contact
S Q16.0 // Set Output
)MCR // Close MCR
AN M5.5 // Emerg.Contact
AN I4.7 // Emerg.Contact
= M69.0 // Output Coil
MCRD // Deactivate
STL
MCR The Master Control Relay is a logical master switch for activating and deactivating power flow. An interrupted path represents a sequence that writes a zero value in place of a calculated value or a sequence that does not change the existing memory value.
Examples If the MCR condition is not fulfilled:
• "0" is assigned via the output coils
• the "Set Coil" and "Reset Coil" instructions do not change the existing value
• the “MOVE” instruction transfers the value zero to the specified destination.
MCRA The MCRA instruction activates the Master Control Relay function.
MCR( “MCR(“ opens an MCR area and triggers an instruction that shifts the RLO to
(for STL) the MCR stack. The stack can have up to eight entries. This means that up to eight individual control areas can be nested between the “MCRA” and “MCRD” instructions.
)MCR The “)MCR“ instruction marks the end of an MCR area.
(for STL)
MCRD The "Deactivate Master Control Relay” instruction deactivates the MCR function. No more MCR areas can be opened until another “MCRA” instruction is given.

18. Unconditional Jump (Independent of RLO)
( JMP )
NEW1
Network 1
Network 2 :
Network x
( )
M69.0
I4.7
M5.5
LAD
NEW1
JMP
....
&
M5.5
I 4.7 =
M69.0
Network 1
Network 2 :
Network x
FBD
Network 1
JU NEW1
Network 2 :
Network x
NEW1: AN M5.5
AN I4.7
= M69.0
STL
Jump Instruction In LAD/FBD, the label is entered as an identifier above the coil symbol or assignment symbol. In STL it comes after the Jump instruction.
The label can have up to four characters, the first of which must be a letter or the “_” character.
The label marks the point where execution of the program is to continue. Any instructions or networks between the jump instruction and the label are not executed.
Jumps can be made both forwards and backwards. The jump instruction and the jump destination must both be in the same block (max. jump length = 64kbyte). The jump destination must only be present once in the block.
Jump instructions can be used in FBs, FCs and OBs.
Inserting In LAD aund FBD, you use the Program Elements browser to insert a label:
a Label Program Elements -> Logic Control / Jump -> Label.
In STL, you enter the label to the left of the statement, from which program exeuction is to continue.
JMP An unconditional jump instruction causes a program jump to a label regardless of the RLO.

19. Conditional Jump (Dependent on RLO)
LAD
FBD
STL
A I0.0
A I0.1
JC NEW1
NEW1
I 0.0
I 0.1
&
I0.0
I0.1
JMP
(JMP)
Jump if
RLO=1
A I0.2
A I0.3
JCN NEW2
JMPN
I0.2
I0.3
NEW2
I 0.2
I 0.3
Jump if
RLO=0
(JMPN)
&
JC The conditional jump “JC” is only executed if the RLO is “1”. If the RLO is “0”, the jump is not executed, the RLO is set to “1” and program execution continues with the next instruction.
JCN The conditional jump “JCN” is only executed if the RLO is "0". If the RLO is "1", the jump is not executed and program execution continues with the next instruction.
Note STL provides additional jump operations, which are discussed in another programming course.

20. RLO - Edge Detection P N LAD P = & N FBD STL I1.0 I1.1 M1.0 M8.0 M1.1
A I1.0
A I1.1
FP M1.0
= M8.0
A I 1.0 A I 1.1 FN M1.1 = M8.1
STL
OB1-Cycle
I1.0
I1.1
RLO
M1.0
M8.0
M8.1
M1.1
Example
RLO Edge An "RLO edge" is when the result of a logic operation changes.
Positive Edge When the RLO changes from “0” to “1”, the "FP" check instruction results in signal state "1" (e.g. at M 8.0) for one cycle.
To enable the system to detect the edge change, the RLO must also be saved in an FP bit memory, or data bit (e.g. M 1.0).
Negative Edge When the RLO changes from “1” to “0”, the "FN" check instruction results in signal state “1” (e.g. at M 8.1) for one cycle.
To enable the system to detect the edge change, the RLO must also be saved in an FN bit memory, or data bit (e.g. M 1.1).

21. Signal - Edge Detection
M8.0
POS
M_BIT
M1.0 Q
I1.0
M8.1
NEG
M1.1
LAD
I1.1 =
M8.0
POS
M_BIT
M1.0
&
I1.0
M8.1
NEG
M1.1
FBD
A I1.0
A (
A I1.1
FP M1.0 )
= M8.0
A (
A I1.1
FN M1.1
= M8.1
STL
I1.0
I1.1
Example
Signal Edge A "signal edge" is when a signal changes its state.
Example Input I 1.0 acts as a static Enable. Input I 1.1 is to be monitored dynamically and every signal change is to be detected.
Positive Edge When the signal state at I 1.1 changes from “0” to “1”, the "POS" check instruction results in signal state "1" at output Q for one cycle, provided input I 1.0 also has signal state "1" (as in the example above).
To enable the system to detect the edge change, the signal state of I 1.1 must also be saved in an M_BIT (bit memory or data bit) (e.g. M 1.0).
Negative Edge When the signal state at I 1.1 changes from “1” to “0” , the "NEG" check instruction results in signal state "1" at output Q for one cycle, provided input I 1.0 has signal state "1" (as in the example above).
To enable the system to detect the edge change, the signal state of I 1.1 must also be saved in an M_BIT (bit memory or data bit) (e.g. M 1.1).
M1.0
M1.1
OB1-Cycle
M8.0
M8.1

22. Exercise: Program for a Bottling Plant (Mode Selection)
Plant ON/OFF:
Manual/Automatic mode:
I 0.0 =
Start (Mom.-cont. switch with NO function)
I 0.4 =
Manual/Automatic (Switch)
I 0.1 =
Stop (Mom.-cont. switch with NC function)
I 0.5 =
Adopt mode (Momentary-
contact switch, NO function)
I 0.2 =
Jog forward (M-C sw., NO funct.)
I 0.3 =
Jog backward (M-C sw., NO func.)
Bottle
sensor
I 16.6 (I 8.6)
Task Write a mode section of a program for a bottling plant to meet the following specifications:
• Input I 0.0 (momentary-contact switch with NO function) switches the plant ON.
• Input I 0.1 (momentary-contact switch with NC function) switches the plant OFF.
• When the plant is ON, the indicator at output Q 8.1 (Q 4.1) is lit.
• When the plant is ON, the operating mode can be selected: - Manual mode is selected when I 0.4=0 and automatic mode when I 0.4= The selected mode is adopted with a pulse at input I 0.5 .
• The indicators for the selected mode are as follows: Manual = Q 8.2 (Q 4.2), Automatic = Q 8.3 (Q 4.3).
• When the mode is changed or the plant is switched off, the mode previously selected must be deselected.
• In manual mode, the conveyor can be jogged forwards with the momentary- contact switch I 0.2 (Q 20.5 / Q 8.5) and backwards with I 0.3 (Q 20.6 / Q 8.6).
What to Do 1. Draft out the program for controlling the operating modes. Use the I/O addresses and field devices shown in the diagram.
2. Create an S7 program with the name "FILL" in the project "My Project".
3. Write the mode section of the program for the bottling plant in block FC 15.
4. Open (off-line) the OB1 and enter a call to FC15 (in STL with the statement “CALL FC 15”).
5. Save your program, download it and test it on the training unit.
Result It should work. M
Q 20.5 (Q 8.5) Conveyor forwards
Q 20.6 (Q 8.6) Conveyor backwards