1. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 6: Procedural Modeling Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#2 Due Today l HW#3 Due in 1 week l Tip for Debugging: » Use workspace directories (we have read access) » Post to message board with the path to your code and the text of the error message(s)

3. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l Does every numeric value have a corresponding logical value? l How do you tell the difference between a bitwise operator and a reduction operator? l How are vectors extended when operand lengths are mismatched? l What operator would you use to implement sign- extension?

4. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Sign-Extending Shifter Example l Intro to Procedural Modeling l Control Constructs l Inferred Latches

5. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Sign-Extending Right Shifter l Design a Module that shifts a 4-bit input to the right 0 to 3 bits, depending on a shift input. l Use only replication and conditional operators: insout 10100 11101 21110 31111

6. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Schematic for the Right-Shifter

7. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Sign-Extending Right Shifter module rightshift(output [3:0] out,input [3:0] in, input [1:0] s); endmodule // rightshift

8. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Today’s Lecture l Sign-Extending Shifter Example l Intro to Procedural Modeling l Control Constructs l Inferred Latches

9. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Parts of a Verilog Module l Header: module ( ); l Parameter, Port, & Variable declarations l Functionality description » Structural –Instantiations of basic gates –Instantiations of lower-level modules » Behavioral –Data-Flow (continuous assignments) –Procedural (initial & always blocks) l Terminator: endmodule

10. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Why Procedural Modeling? l Needed for test-benches l Can also use it to describe the hardware. Why would we want to? » Needed to describe sequential logic » What is sequential logic?

11. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Modeling Combinational Logic l Generally, combinational logic is modeled with continuous assignments (Data-Flow modeling)… l …But it can also be modeled procedurally » More abstract than Data-Flow » Allows the use of “control constructs” like if-then-else, case

12. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Initial Blocks l You’re familiar with procedural blocks… You used one to implement a test bench: l Procedural blocks are special because the statements are assumed to be executed sequentially l Unlike the Data-Flow (continuous assignment), for which the order doesn’t matter initial begin $monitor($time, “in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 0;// vector #1 #10 in0 = 0; in1 = 1; sel = 1;// vector #2 #10 $finish; end

13. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 A Simple Procedural Example l Assuming that A,B,C, and X are all 1-bit variables, what logic is implied by the procedural behavior below? l If we had written this as a dataflow behavior, it would be illegal. Why? assign X=A&B; assign X=(X==C); X=A&B; X=(X==C);

14. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 The always Block l Use the following statement to define a procedural hardware block: always @( ) or where is a sequence of assignments delimited by begin and end l The or “sensitivity list” gives the events that “trigger” the execution of the block

15. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Event-Lists l Simply naming a variable in the event-list means that the block will be triggered whenever that variable changes l Use the or keyword to list multiple variables l In this example, what does the event-list need to be for the logic to behave as expected? always @( ) begin X=A&B; X=(X==C); end

16. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Verilog 2001 Event-Lists l Verilog 2001 allows the use of commas to separate events l The special case of @(*) or @* can be used to indicate “all signals referenced in any expression” always @( ) begin X=A&B; X=(X==C); end always @( ) begin X=A&B; X=(X==C); end

17. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Incomplete Sensitivity Lists l If we had written the block like this, what would happen? l All combinational inputs MUST be in the event- list for the logic to be modeled properly! always @( A ) begin X=A&B; X=(X==C); end

18. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 A Complete Procedural Module l Remember that assignments in proceudural block must be to reg variables! (not wire variables) l Otherwise, you’ll get an error. l Synthesis tools will recognize that combinational logic is being modeled, and there will be no registers in the final hardware. module and_xnor(X, A, B, C); input A, B, C; output X; reg X; always @( A or B or C ) begin X=A&B; X=(X==C); end endmodule // and_xnor

19. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 A Complete 2001 Procedural Module l Note that the output X is declared as a reg inside the port-list l Note the use of @* (This is always advised when modeling combinational logic, in order to avoid the incomplete sensitivity list problem) module and_xnor( output reg X, input A, B, C); always @* begin X=A&B; X=(X==C); end endmodule // and_xnor

20. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Today’s Lecture l Sign-Extending Shifter Example l Intro to Procedural Modeling l Control Constructs l Inferred Latches

21. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Conditional Statements: if-else if - else if - else has the following syntax. if ( ) ; else if ( ) ; else ; If the logical value of is true, is executed. If the logical value of is false and the logical value of is true then is executed. If the logical values of both and are false, then is executed. Sutherland guide 10.3

22. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 ALU Example: if-else Code fragment of a 16-bit arithmetic logic unit (ALU) that performs one of 5 operations. if (alu_ctrl == 0) // alu_ctrl is 3 bits ALU_OUT = ALU_IN1 + ALU_IN2;// add else if (alu_ctrl == 1) ALU_OUT = ALU_IN1 - ALU_IN2;// subtract else if (alu_ctrl == 2) ALU_OUT = ALU_IN1 & ALU_IN2;// and else if (alu_ctrl == 3) ALU_OUT = ALU_IN1 | ALU_IN2;// or else if (alu_ctrl == 4) ALU_OUT = ALU_IN1 ^ ALU_IN2;// exor else ALU_OUT = 16’d0;// other 3 undefined

23. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Conditional Statements: case The syntax of the case statement is: case ( ) : ; : ; default: ; endcase The value of is matched to in sequence, For the first that matches, the corresponding is executed. If no alternatives match, is executed. Sutherland guide 10.3

24. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 ALU Example: case Using the previous example of an ALU, the corresponding implementation using a case statement is: case (alu_ctrl) 3’d0: ALU_OUT = ALU_IN1 + ALU_IN2; 3’d1: ALU_OUT = ALU_IN1 - ALU_IN2; 3’d2: ALU_OUT = ALU_IN1 & ALU_IN2; 3’d3: ALU_OUT = ALU_IN1 | ALU_IN2; 3’d4: ALU_OUT = ALU_IN1 ^ ALU_IN2; default: ALU_OUT = 16’d0;

25. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 case: Comparison Details The case statement literally compares 0, 1, x and z values in the conditional expression bit-by-bit with the alternatives. Thus if the case expression is 4’b10xz, the comparison is looking for an alternative of 4’b10xz. In other words an exact match is required. Also, if the sizes of the evaluated expression and the alternative pattern are unequal, the shortest field is extended with zeros so the sizes are equal.

26. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 Alternatives: casex, casez There are two variants of the case statement defined by the keywords casex and casez. casex treats all x and z values in the case expression or alternatives as don’t cares. casez treats all z values in the case expression or alternatives as don’t care’s. The casex is useful when the state of certain bit positions is immaterial in some of the alternatives. By using casex in such situations, it is possible to reduce the number of alternatives needed. Sutherland guide 10.3

27. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 Procedural Examples l Muxes and Data Selectors reg [1:0] in1, in2, out; reg in3; always@(in1 or in2 or in3) if (in3) out = in1; else out = in2; in1[0] in2[0] in1[1] in2[1] in3 out[0] out[1] 1010 in1[0] in1[1] in1[2] in1[3] in2 01230123 out reg [3:0] in1; regout; reg [1:0] in2; always@(in1 or in2) case (in2) 2’b00 : out = in1[0]; 2’b01 : out = in1[1]; 2’b10 : out = in1[2]; 2’b11 : out = in1[3]; endcase

28. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 28 Procedural Examples l Priority Selector or Encoder always@(A or B or C) casex(A) 3’b1xx : out = B; 3’b01x : out = C; default : out = 2’b0; endcase l Decoder always@(address) case (address) 2’b00 : line = 4’b0001; 2’b01 : line = 4’b0010; 2’b10 : line = 4’b0100; 2’b11 : line = 4’b1000; endcase A[2] has priority over other bits of A. If A[2]=1, out=B, no matter what. 0123456701234567 00CCBBBB00CCBBBB Out[1:0] 2 A[2:0] 2 address line[3] line[2] line[1] line[0]

29. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 29 Today’s Lecture l Sign-Extending Shifter Example l Intro to Procedural Modeling l Control Constructs l Inferred Latches

30. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 30 Latches l Complete the behavior below: always@(clock or D) if (clock) Q = D; clock D Q l We will not intentionally build latches in this class l Instead, we’ll stick to one type of timing element (edge triggered flip-flops)

31. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 31 Inferred (Unintentional) Latches l What is happening here? always@(A or B or C) begin D = B & C; if (D) E = C; end

32. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 32 Procedural Examples l What about this? always@(A or B) casex (A) 2’b00 : C = B; 2’b01 : C = ~B; endcase

33. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 33 Procedural Examples l Will this simulate correctly? always@(A) C = A | B;

34. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 34 Summary l Does the order of procedural assignments matter? What about continuous assignments? l What does the event-list of an always block mean? l To model combinational logic procedurally, what variables must be in the event list? l Should variables assigned in a procedural block be declared as wire, reg, or either? l How do you prevent an unintentional latch?