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# Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 8: Sequential Design Spring 2009 W. Rhett.

## Presentation on theme: "Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 8: Sequential Design Spring 2009 W. Rhett."— Presentation transcript:

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 8: Sequential Design Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#3 Due Today l Brief Exam Review Tuesday l Exam #1 in 1 Week l HW#4 Due in 2 Weeks

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Today’s Lecture l Sequential Design w/ Simplified Coding Style l Sophisticated Coding Style

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Design Process l Step 1: Write Specification l Step 2: Draw Schematic l Step 3: Write Verilog Code

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Step 1: Write Specification Example: Count Down Timer from the Verilog Simulation Tutorial » 4-bit counter » count value loaded from `in’ on a positive clock edge when `latch’ is high » count value decremented by 1 on a positive clock edge when `dec’ is high » count value cleared when ‘clear’ is high » decrement stops at 0 » `zero’ flag active high whenever count value is 0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Step 2: Draw a Block Diagram l Identify from the Specification: » Ports » Registers » Datapath Logic » MUXes » Control Logic l ALWAYS DRAW A BLOCK DIAGRAM OR SCHEMATIC BEFORE CODING

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Identify Ports l 4-bit counter l count value loaded from `in’ on a positive clock edge when `latch’ is high l count value decremented by 1 on a positive clock edge when `dec’ is high l count value cleared when ‘clear’ is high l decrement stops at 0 l `zero’ flag active high whenever count value is 0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Identify Registers l 4-bit counter l count value loaded from `in’ on a positive clock edge when `latch’ is high l count value decremented by 1 on a positive clock edge when `dec’ is high l count value cleared when ‘clear’ is high l decrement stops at 0 l `zero’ flag active high whenever count value is 0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Identify Datapath Logic l 4-bit counter l count value loaded from `in’ on a positive clock edge when `latch’ is high l count value decremented by 1 on a positive clock edge when `dec’ is high l count value cleared when ‘clear’ is high l decrement stops at 0 l `zero’ flag active high whenever count value is 0 l How would you implement the ==0? logic?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Identify MUXes l 4-bit counter l count value loaded from `in’ on a positive clock edge when `latch’ is high l count value decremented by 1 on a positive clock edge when `dec’ is high l count value cleared when ‘clear’ is high l decrement stops at 0 l `zero’ flag active high whenever count value is 0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Identify Control Logic l 4-bit counter l count value loaded from `in’ on a positive clock edge when `latch’ is high l count value decremented by 1 on a positive clock edge when `dec’ is high l count value cleared when ‘clear’ is high l decrement stops at 0 l `zero’ flag active high whenever count value is 0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Step 3: Write the Verilog Code l Name the internal signals l Write the description into code » Ports & internal signals » Registers » Datapath Logic » MUXes » Control Logic l Never write a piece of code if you can’t visualize the logic that it implements

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Simplified Verilog Style l Verilog is a powerful and flexible language » It is very easy to describe functions that do NOT map well (or synthesize into) hardware l Constrain yourself to a subset of the language and a specific style of usage : Registers: always@(posedge clock) begin register_output1 <= register_input1; register_output2 <= register_input2; end MUXes and Control Logic: always@(input1 or input2 or...) begin end Datapath Logic: assign output =

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Name the Internal Signals

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Complete Verilog Code module counter (clock, in, latch, dec, clear, zero); /* simple top down counter with zero flag */ input clock; /* clock */ input [3:0] in; /* starting count */ input latch; /* latch `in’ when high */ input dec; /* decrement count when dec high */ input clear; /* clear count when clear high */ output zero; /* high when count down to zero */ reg [3:0] value; /* current count value */ reg [3:0] next_value; wire zero, enable; // D-Flip Flops with enable always@(posedge clock) if (enable) value <= next_value; // produce enable assign enable = latch | (dec & !zero) | clear; // input multiplexor to value register always@(latch or value or in or dec or zero) begin if (latch) next_value = in; else if (dec && !zero) next_value = value - 1’b1; else next_value = 4’b0; // default is clear end // combinational logic to produce `zero’ flag assign zero = ~|value; endmodule /* counter */

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 always@(posedge clock) if (enable) value <= next_value; assign enable = latch | (dec & !zero) | clear; always@(latch or value or in or dec or zero) begin if (latch) next_value = in; else if (dec && !zero) next_value = value - 1’b1; else next_value = 4’b0; // default is clear end assign zero = ~|value;

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Today’s Lecture l Sequential Design w/ Simplified Coding Style l Sophisticated Coding Style

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Sophisticated Style l Combine registers and as much combinational logic as you can into one always@(posedge clock) block always@(posedge clock) begin if (latch) value <= in; else if (dec && !zero) value <= value - 1’b1; else value <= 4’b0; // default is clear end assign zero = ~|value;

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Comparison of Styles Simplified StyleSophisticated Style How many internal signals needed to be defined? How many lines of code? (including spaces) How many separate always blocks and assign statements? With the Sophisticated style, you’ll write descriptions faster.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Comparison of Styles Simplified StyleSophisticated Style How can you tell from the code where the flip-flops are? Do you need to worry about whether an assignment is blocking or non- blocking? With the Sophisticated style, it’s easier to make errors in your code

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Summary l How do you infer flip-flops for an always@(posedge clock) procedure with blocking or non-blocking assignments? l Is it better to use blocking or non-blocking assignments in an always@(posedge clock) procedure? Why? l What are the key elements of the “simplified coding stlye”? l What Verilog constructs do you use to describe » MUXes » Control logic » Datapath logic » Registers l What would happen if you assigned the “zero” signal inside the always@(posedge clock) block in the “sophisticated style” example?

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