1. Surfliner: Distortion-less Electrical Signaling for Speed of Light On- chip Communication Hongyu Chen, Rui Shi, Chung-Kuan Cheng Computer Science and Engineering University of California, San Diego David M. Harris Harvey Mudd College

2. Outline Introduction Surfliner Overview Theory Implementation Simulation Results Applications Conclusions

3. Introduction On-chip Global Interconnect trend Major Concerns: Speed, Power, Cost

4. Introduction ITRS roadmap: Wall of Global Interconnect Delay (Speed of Light 5ps/mm) Power Density (> ½) Clock Skew:Variations (5GHz) Wire optimization is getting harder and harder !

5. Introduction Existing on-chip signaling techniques Pre-emphasis and Equalization, Dally, VLSI 1998 Modulating to High-frequency domain; S. Wong, JSSC 2003. Non-linear transmission line; Afshari, Hajimiri, CICC 2003. Differential pair with discharging scheme, Horowitz, SVLSI 2003

6. Previous Works Modulating to High-frequency domain; S. Wong, JSSC 2003.

7. Previous works Differential pair with discharging scheme, Horowitz, SVLSI 2003

8. Surfliner - Overview Speed-of-the-light on-chip communication < 1/5 Delay of Traditional Wires Low Power Consumption < 1/5 Power Consumption Robust against process variations Short Latency Insensitive to Feature Size

9. Surfliner - Theory Differential Lossy Transmission LineSurfliner Current loss through shunt capacitance Frequency dependent phase velocity (speed) and attenuation Add shunt conductance to compensate current loss R/G = L/C Flat from DC Mode to Giga Hz Telegraph Cable: O. Heaviside in 1887.

10. Theory (Telegrapher’s Equation) Telegrapher’s equation: Propagation Constant: Wave Propagation: Alpha and Beta corresponds to attenuation and phase velocity. Both are frequency dependant

11. Theory (Distortionless Line) Set G=RC/L Frequency Independent speed and attenuation: Characteristic impedance: (pure resistive) Phase Velocity (Speed of light in the media) Attenuation:

12. Digital Signal Response

13. Eye Diagram Injected 1.0V voltage falls to 365mv over a 2cm wire 120 stage, 2.1ps jitter

14. Speed, Power, Variations Speed of Light: 5ps/mm or 50ps/cm Power: 10mW at >GHz Conductance variation = 10%, f=10MHz~10GHz Phase velocity variation < 1% Attenuation variation < 1%

15. Implementation Add shunt conductance between differential wires Resistors realized by serpentine unsilicided poly, diffusion resistors, or high resistive metal

16. Simulation Results Configuration of wires Characteristic Impedance (at 10GHz) : 39.915 Ohm Inductance: 0.22nH/mm Capacitance: 141fF/mm Attenuation: 253mv magnitude at receiver’s end (assuming 1V at sender’s end) Using Microstrip (free space above the wires): impedance can be improved to 52.8Ohm

17. Simulation Results (Settings) Agilent ADS Momentum extract 4-port S- parameters HSpice: Transient analysis Assume 1023 bit pseudo random bit sequence (PRBS) 15GHz clock 10% of clock period transition slope for each rising and falling edge

18. Simulation Results 4 Stages 120 Stages

19. Simulation Results Jitter and silicon area usage #Stages410204080120160 Jitter (ps)279.55.44.23.92.12.08 Area (um 2 )0.523.2513.052208468832 Power w/ different width and separation (w, s) (um)(3,3)(4,4)(5,4)(10,5) Power (mW)4.983.623.022.13 Attenuation0.3070.4150.4960.60

20. Applications of Surfliner 1.Clock distributions 2. Data communications: Buses Between CPUs, DSPs, Memory Banks

21. Application of Surfliner 3. High Performance Low Power Wafer Packaging

22. Conclusions Feasibility of Implementing Distortionless Transmission Line for On-Chip Communication Advantages of Surfliner Speed of Light Low Power (independent with data rate) High throughput Limitation of Surfliner Require wide metal wires Static power consumption

23. Conclusions Applications Global data communication High Speed Clock Wafer Scale Packaging Future Directions Explore the design space of wire configurations and sender/receiver circuitry Quantify the design trade-offs for surfliner Innovative communication architectures