1. Clock Distribution Scheme using Coplanar Transmission Lines Victor Cordero Sunil P Khatri Department of ECE Texas A&M University vcordero@ece.tamu.edu sunilkhatri@tamu.edu

2. Introduction Traditional clocking scheme –Not suitable for high frequency i.e. high gigahertz range of operation –Also, power dissipation is high since charge is not recovered Exploiting On chip inductance –High speed interconnect has inductive nature i.e. clock network has inherent LC characteristic –Clock networks become resonant circuits –Methods of managing energy on the transmission lines Standing Waves Travelling Waves

3. Classic Rotary Wave Oscillator Inverters switch as the wavefront travels Voltage wave inverts during consecutive rotations, and each arbitrary location provides a 50% duty cycle, which is used as system clock. Oscillation with energy recovery (2 laps required for one period)

4. The Phase Shift Problem

5. Questions to Classic Rotary Clock 1)Why do we need to propagate a square wave? Can we “encode” a clock in a differential pair more efficiently? 2) Can we get phase = 0 at all points along the ring regardless of distance? 3) How to tap into (“decode”) the clock signal from the transmission line ring?

6. Standing Wave Oscillators λ/4 standing wave oscillation Forward waves (from inverter) travels along the transmission line, hits the short and gets a reverse wave back Forward and reverse superpose and we obtain a standing wave along Z direction Sinusoid wave propagation Z Z

7. Short Terminated Ring Differential Line Total Linear Length = 1567.2 um Each segment 65.3um long 25 probe locations, each with full differential amplifier and load cap (5 not used) Used a 90 nm technology (BSIM3) (1V) Simulated in HSPICE Corner effect assumed negligible Single sided voltage polarity per half cycle across ring

8. Short – Termination Results Avg power = 7.5756mW (incl 25 square wave recoverers) Overlap plot of recovered clock at 20 distributed locations Max skew (rising edge) = 6ps (last 5 segments unusable for recovery) Frequency oscillation = 4Ghz (Period 250ps) Overlap plot of probed ring locations. All nets very similar “zero” crossing location Complex shaped standing wave

9. Our Contribution : Differential Mobius T-line Replace short connect to a mobius interconect at the end of TL Can we go faster for the same total length? We create a “virtual” short at the halfpoint from the source We create a two phase system. Flip differential amplifier connections on the left side to get same phase for recovered clock

10. Our Differential Mobius Design Avg power = 8.201mW (including 25 square wave recoverers) Max skew (rising edge) = 3.1ps (middle 4 segments unusable for recovery) Frequency oscillation = 9.8Ghz (Period 101.9ps). Duty cycle <50%

11. Mobius Versus Short-Termination Mobius termination works at 9GHz, while Short-circuit termination works at 4GHz. Why? –Short termination has a significant impedance mismatch Hence a spurious traveling wave results. –Mobius termination has a lower impedance mismatch at the end- point. This mismatch is due to the presence of the cross-coupled inverter pair, but not due to short circuit termination. The spurious traveling wave has lower amplitude than in the short- circuit termination case Short Termination Mobius Termination

12. Our Clock Recovery Circuit Differential input 2 VDC ~=0.5v VAC~0.6v to 40mV (very wide range able) Differential input 1 Current mirror Bias generator Sharp edge generators and buffer 1V Min size to loading in gates.and to cascaded inverters

13. Loading Effect with Mobius Variation of frequency versus number of probing points Variation of points near the virtual short affects the oscillation frequency the most We add tapping points systematically, from the first segment to the last segment. (Base configuration: Wp = 300um, Wp/Wn = 2.4, T-line width = 20um, Tline width= 20um, Tline thick = 2um, and Tline elevation to substrate = 20um ) Good tolerance to number of tapping points (less than 0.11% global frequency variation)

14. Long ring configurations Total ring length (um) T-line width (um) Wp (um) Beta (wp/wn) Freq (GHz) Global Skew max (ps) Power (mW)Non recoverable nodes 4927.2401202.49.0900.9863.6403 5407.2401002.09.0222.8703.4003 5407.2401002.19.0752.993.3003 5407.2401002.49.2663.313.1203 Our Standing wave Clock configurations Standard Rotary Clock configurations Total ring length (um) T-line width (um) Wp (um) Beta (wp/wn) Freq (GHz) Global Skew max (ps) Power (mW) Non recoverable nodes 4927.2401202.43.68253.543 5407.2401002.03.808.13.282 5407.2401002.13.897.863.092 5407.2401002.44.0711.32.911 Total ring length (um) T-line width (um) Wp (um) Beta (wp/wn) Freq (GHz) Power con­ sumed (mW) 4927.220101.227.972.49 5407.230101.027.752.57 5407.220101.227.512.46 5407.225100.97.342.81 Shorted wave Clock configurations For rotary wave a sweep was performed in order to track the maximum achievable frequency for the studied length (at 25 repeater pairs)

15. Design Cookbook We performed extensive experiments with varying –Conductor widths –Ring length –Inverter size –PMOS to NMOS size ratio Details are in the paper

16. Summary We have developed an improved resonant clock architecture by eliminating the phase shift complexity (of the Rotary Clock) across the ring Our ring structure maintains a single standing wave with a virtual short. –Doubles operating frequency compared to a standing wave oscillator with a short circuit termination We developed custom high speed differential to square wave amplifiers for the wide range of tapping point types along the ring. The clock recovery adds almost no loading effect on the differential transmission line Studied the performance of our architecture as a function of various circuit parameters.

17. Thank you!

18. Considerations at 9GHZ We could double the total loop length (when using mobius) and keep the same frequency as the shorted loop (for bigger chips) Output of the clock not fully square wave due to our CMOS inverter performance in high frequency. Variable falling edge due to decreased swing at differential stage for “weak” probe points The cascaded output inverter stage (of the clock recovery circuit) has a hard time creating sharp square edges at 9Ghz.

19. Ring Length Effects in Mobius If length is too long, the standing wave won’t form. If high frequencies required we can link multiple standing wave rings The architecture allows us to have scalable frequencies by simply adjusting the total ring length within a range With 25 recovery circuits Without recovery circuits With 25 recovery circuits

20. Ring Width Effects in Mobius If we increase wire resistance, more energy needed to keep oscillation going. W<= 20um Power consumption monotonically decreases until to W=24um W>= 20um Ring configuration stays the same as before. Fully tapped ring used. W>= 20um

21. PMOS/NMOS width effects Power consumpion grows close to linear when PMOS width grows. Bigger drivers increase our total ring capacitance, making the oscillation frequency drop Max skew gets reduced by stronger drivers.

22. PMOS Width/NMOS Width effect High Wp/Wn ratio increases our oscillation frequency, however above 3.5 it begins to raise our skew Maximum skew is approximately flat within a Wp/Wn ratio range.

23. Future Work Perform EM characterization on the mobius ring to get insight on how 90 degree corners affect the design performance Experiment with temperature and voltage supply variations. Design a PVT resilient cross coupled inverter pair. Experiment on interlocking rings while keeping zero phase shift across them Implement the design in an advanced fabrication process

24. Current on-going work Frequency stepping. Direct tuning of the frecuency through modification of the ring capacitance. This provides wide range of frequency stepping