1. Chapter 3: Computer Organization Fundamentals
Prof. Ben Lee
Oregon State University
School of Electrical Engineering and Computer Science

2. Chapter Goals
Understand the organization of a computer system and its components.
Understand how assembly instructions are executed on the processor.
Ch. 3: Computer Organization Fundamentals

3. Computer Organization
Ch. 3: Computer Organization Fundamentals

4. Memory Random Access Memory Holds instrutions (program) and data
Unified
Separate instruction and data memory
Organized into consecutive addressable memory words.
1 memory word
Memory data size
Size of the information accessed by the CPU (CPU register size)
Manufacturer’s definition
Ch. 3: Computer Organization Fundamentals

5. Registers Some important registers:
PC (Program Counter) – holds the address of the next inst. to be fetched from memory
MAR (Memory Address Register) – holds the address of the next instruction or data to be fetched from memory.
MDR (Memory Data Register) – hold the information (word) to be sent to/from memory.
AC (accumulator) – a special register which holds the data to be manipulated by the ALU.
IR (Instruction Register) – holds the instruction to be decoded by the Control Unit (CU).
Ch. 3: Computer Organization Fundamentals

6. A Pseudo-CPU opcode address Instruction Format ALU …
To/from memory and I/O devices
Internal
control
signals
External
Internal Data Bus AC IR PC
MDR
MAR CU +1
Ch. 3: Computer Organization Fundamentals

7. Bus-Register Connections
Internal Data Bus
Enable
Output
Register
CLK
Tri-State Buffer
Enable Input Out
0 X Hi-Z
1 0 0
1 1 1
Input
Enable
Ch. 3: Computer Organization Fundamentals

8. Bus-Register Connections
Internal Data Bus
Enable
Output
Tri-State Buffer
Enable Input Out
0 X Hi-Z
1 0 0
1 1 1
Register
CLK
Input
Enable
MUX
0 1
Select
To ALU/Memory
From ALU/Memory
Ch. 3: Computer Organization Fundamentals

9. Fetch and Execute Cycle
A series of steps (i.e., micro-operations) a computer takes to fetch and execute one instruction.
Each micro-operation requires a clock cycle.
Fetch and execute cycle => Instruction Cycle.
Number of micro-operations required to fetch an instruction is usually the same.
Number of micro-operations required to execute each instruction differs depending on
Complexity of the instruction
e.g., Multiply takes longer than Add
Available hardware
e.g., Multiplier vs. no multiplier hardware
Ch. 3: Computer Organization Fundamentals

10. Fetch Cycle Need to describe what has to happen in each cycle.
Will use register transfer operations to describe the movement of data.
Fetch Cycle
Step 1: MAR  PC
Step 2: MDR  M(MAR) ; Transfer the content of memory
; pointed to by MAR
Step 3: IR  MDR (opcode), MAR  MDR (address)
Step 4: PC  PC + 1
Go to beginning of Execute cycle
Note: Steps 2 and 4 can be performed at the same time.
Ch. 3: Computer Organization Fundamentals

11. Fetch Cycle (Step 1) Step 1: MAR  PC … … opcode address
Instruction Format
ALU
Step 1: MAR  PC AC
Internal Data Bus
PC_OUTenable IR +1 PC PC
MARenable PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
opcode
address
Instruction
External
control
signals …
Ch. 3: Computer Organization Fundamentals

12. Fetch Cycle (Step 2) Step 2: MDR  M(MAR), PC  PC + 1 … … opcode
address
Instruction Format
ALU
Step 2: MDR  M(MAR), PC  PC + 1 AC
Internal Data Bus IR
PCenable
MDRenable +1 PC
PC+1
Instruction PC PC
MDR
MAR
Read
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
opcode
address
Instruction
External
control
signals …
Ch. 3: Computer Organization Fundamentals

13. Fetch Cycle (Step 3) Step 3: IR  MDR (opcode), MAR  MDR (address) …
Instruction Format
ALU
Step 3: IR  MDR (opcode), MAR  MDR (address) AC
Internal Data Bus IR
MDR_OUTenable
IRenable
opcode +1
PC+1
Instruction
address PC
MARenable PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
opcode
address
Instruction
External
control
signals …
Ch. 3: Computer Organization Fundamentals

14. Execute Cycle Execute cycle depends on the instruction
Will describe execute cycle based on the following basic instruction:
Data transfer Instructions
LDA x (Load Accumulator)
STA x (Store Accumulator)
Arithmetic and Logical Instructions
ADD x (Add to accumulator)
Control Transfer
J x (Jump to x)
BNE x (Branch conditionally to x)
Ch. 3: Computer Organization Fundamentals

15. Execute Cycle Example: LDA x (Load Accumulator) Execute Cycle
Step 1: MDR  M(MAR)
Step 2: AC  MDR
Return to the beginning of the instruction cycle
Memory … PC
LDA x
Instruction … AC x
Operand
=>
Operand …
Ch. 3: Computer Organization Fundamentals

16. Execute Cycle (Step 1) Step 1: MDR  M(MAR) … … opcode address
Instruction Format
ALU
LDA x
Step 1: MDR  M(MAR) AC
Internal Data Bus IR
MDRenable
LDA +1
PC+1
Operand
Instruction x PC
MDR
MAR
Read
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
LDA x
Instruction
External
control
signals … x
Operand
Ch. 3: Computer Organization Fundamentals …

17. Execute Cycle (Step 2) Step 2: AC  MDR … … opcode address
Instruction Format
ALU
LDA x
Step 2: AC  MDR AC
ACenable
Operand
Internal Data Bus
MDR_OUTenable IR
LDA +1
PC+1
Operand x PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
LDA x
Instruction
External
control
signals … x
Operand
Ch. 3: Computer Organization Fundamentals

18. Execute Cycle Example: STA x (Store Accumulator) Execute Cycle
Step 1: MDR  AC
Step 2: M(MAR)  MDR
Return to the beginning of the instruction cycle
Memory … PC
STA x
Instruction … AC x
Operand
<=
Operand …
Ch. 3: Computer Organization Fundamentals

19. Execute Cycle (Step 1) Step 1: MDR  AC … … opcode address
Instruction Format
ALU
STA x
Step 1: MDR  AC AC
Operand
Internal Data Bus
AC_OUTenable IR
MDRenable
STA +1
PC+1
Instruction
Operand x PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
STA x
Instruction
External
control
signals … x
Ch. 3: Computer Organization Fundamentals …

20. Execute Cycle (Step 2) Step 2: M(MAR)  MDR … … … … opcode address
Instruction Format
ALU
STA x
Step 2: M(MAR)  MDR AC
Operand
Internal Data Bus IR
MDRenable
STA +1
PC+1
Operand x PC
MDR
MAR
Write
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
STA x
Instruction
External
control
signals … x
Operand
Ch. 3: Computer Organization Fundamentals

21. Execute Cycle Example: ADD x (Add to Accumulator) Execute Cycle
Step 1: MDR  M(MAR) ; Read operand
Step 2: AC  AC + MDR ; Add and transfer result to AC
Return to the beginning of the instruction cycle
Effective Address - address that points to the operand
Memory … PC
ADD x
Instruction … AC x
Operand2 +
Result
Operand1 …
Ch. 3: Computer Organization Fundamentals

22. Execute Cycle (Step 1) Step 1: MDR  M(MAR) … … … … … opcode address
Instruction Format
ALU
ADD x
Step 1: MDR  M(MAR) AC
Operand1
Internal Data Bus IR
MDRenable
ADD +1
PC+1
Operand2
Instruction x PC
MDR
MAR
Read
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
ADD x
Instruction
External
control
signals … x
Operand2
Ch. 3: Computer Organization Fundamentals …

23. Execute Cycle (Step 2) Step 2: AC  AC + MDR … … … … opcode address
Instruction Format
ALU
ADD
ADD x
Step 2: AC  AC + MDR AC
ACenable
Result
Operand2
Internal Data Bus
MDR_OUTenable IR
ADD +1
PC+1
Operand2 x PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
ADD x
Instruction
External
control
signals … x
Operand2
Ch. 3: Computer Organization Fundamentals

24. Execute Cycle Example: J x (Jump to x) Execute Cycle
Step 1: PC  MDR(address)
Return to the beginning of the instruction cycle
Memory …
Branch Target Address PC J x … x
Next Instruction
Ch. 3: Computer Organization Fundamentals

25. Execute Cycle (Step 1) Step 1: PC  MDR(address) … … opcode address
Instruction Format
ALU B x
Step 1: PC  MDR(address) AC
Internal Data Bus
MDR_OUTenable IR
PCenable B +1
PC+1 x
Instruction x PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC B x
Instruction
External
control
signals … x
Next Instruction
Ch. 3: Computer Organization Fundamentals

26. Execute Cycle Example: BNE x (Branch Conditionally to x) Execute Cycle
Step 1: If (Z!=1) then PC  MDR(address)
Return to the beginning of the instruction cycle
Memory …
Branch Target Address PC
BNE x … x
Next Instruction
Ch. 3: Computer Organization Fundamentals

27. Execute Cycle (Step 1) Step 1: If (Z!=1) then PC  MDR(address) Z … …
Branch
MDR_OUTenable
PCenable
Z=1 if last ALU operation is zero
opcode
address
Instruction Format
ALU BZ x AC
Step 1: If (Z!=1) then PC  MDR(address)
Internal Data Bus
MDR_OUTenable IR
PCenable BZ +1
PC+1 x
Instruction x PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
BNE x
Instruction
External
control
signals … x
Next Instruction
Ch. 3: Computer Organization Fundamentals

28. One More Example… Example: LDA (x) (Load Accumulator Indirect)
Execute Cycle
Step 1: MDR  M(MAR) ; Read effective address (EA)
Step 2: MAR  MDR ;
Step 3: MDR  M(MAR) ; Read operand
Step 4: AC  MDR ; Move operand to AC
Return to the beginning of the instruction cycle
Memory
Useful for indexing arrays! …
Effective Address - address that points to the operand PC
LDA x
Instruction … x EA … AC EA
Operand
=>
Operand
Ch. 3: Computer Organization Fundamentals

29. Execute Cycle (Step 1) Step 1: MDR  M(MAR) Memory … … opcode address
Instruction Format
ALU
LDA
(x)
Step 1: MDR  M(MAR) AC
Internal Data Bus IR
MDRenable
LDAI +1
PC+1 EA
Instruction x PC
MDR
MAR
Read
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
LDAI x
External
control
signals … x EA … EA
Operand
Ch. 3: Computer Organization Fundamentals

30. Execute Cycle (Step 2) Step 2: MAR  MDR … … opcode address
Instruction Format
ALU
LDA
(x)
Step 2: MAR  MDR AC
Internal Data Bus IR
MDR_OUTenable
LDAI +1
PC+1 EA EA PC x
MARenable PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
LDAI x
External
control
signals … x EA … EA
Operand
Ch. 3: Computer Organization Fundamentals

31. Execute Cycle (Step 3) Step 3: MDR  M(MAR) … … opcode address
Instruction Format
ALU
LDA
(x)
Step 3: MDR  M(MAR) AC
Internal Data Bus IR
MDRenable
LDAI +1
PC+1
Operand EA PC x EA PC
MDR
MAR
Read
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
LDAI x
External
control
signals … x EA … EA
Operand
Ch. 3: Computer Organization Fundamentals

32. Execute Cycle (Step 4) Step 4: AC  MDR … … opcode address
Instruction Format
ALU
LDA
(x)
Step 4: AC  MDR AC
ACenable
Operand
Internal Data Bus
MDR_OUTenable IR
LDAI +1
PC+1
Operand EA PC
MDR
MAR
Instruction
Address
Data
Register Transfers & Control Signals
Legend CU
Internal
control
signals
Memory … … … PC
LDAI x
External
control
signals … x EA … EA
Operand
Ch. 3: Computer Organization Fundamentals

33. Last Example…(I promise!)
Example: LDA -(x) (Load Accumulator Indirect with Pre-decrement)
Useful for stepping through arrays
Execute Cycle
Step 1: MDR  M(MAR) ; Read effective address (EA)
Step 2: MDR  MDR - 1 ; Decrement EA
Step 3: M(MAR)  MDR ; Store it back in x
Step 4: MAR  MDR ;
Step 5: MDR  M(MAR) ; Read operand
Step 6: AC  MDR ; Move operand to AC
Memory … PC
LDAI- x
Instruction … -1 x EA
EA+1 EA … AC EA
Operand
=>
Operand
Ch. 3: Computer Organization Fundamentals

34. Easiest Way Assume MDR can decrement itself Instruction Format ALU …
To/from memory and I/O devices
Internal
control
signals
External
Internal Data Bus AC IR PC
MDR
MAR CU
opcode
address
ADD
-(x) -1
Assume MDR can decrement itself +1
Ch. 3: Computer Organization Fundamentals

35. Hard Way Must use AC and ALU!
Instruction Format
TEMP
ALU …
To/from memory and I/O devices
Internal
control
signals
External
Internal Data Bus AC IR PC
MDR
MAR CU +1
opcode
address
ADD
-(x)
Must use AC and ALU!
Need a TEMP register to store previous content of AC
Ch. 3: Computer Organization Fundamentals

36. Hard Way MDR doe not have the capability to decrement itself.
So must use ALU through AC.
AC needs to be saved so that it is not overwritten.
Execute Cycle
Step 1: MDR  M(MAR) ; Read effective address (EA)
Step 2: Temp  AC ; Save AC in Temp
Step 3: AC  MDR ;
Step 4: AC  AC - 1 ; Decrement EA
Step 5: MDR  AC
Step 6: AC  Temp ; Restore AC
Step 7: M(MAR)  MDR ; Store it back in x
Step 8: MAR  MDR ;
Step 9: MDR  M(MAR) ; Read operand
Step 10: AC  MDR ; Move operand to AC
Can you think of a way to perform LDA (x)+ (Load Accumulator Indirect with Post-increment)?
Ch. 3: Computer Organization Fundamentals

37. What We Will See Later… AVR Microcontroller
Used in low-end embedded systems
Ch. 3: Computer Organization Fundamentals

38. What You Will See in ECE 472…
5-stage pipeline
Used in high-end embedded systems, e.g., Mobile devices.
Ch. 3: Computer Organization Fundamentals

39. What You Will See in ECE 570…
SuperScalar
OoO (out-of-order execution)
Speculation
Used in PCs and servers.
Branch
Prediction
Instruction
Cache
Fetch
Instruction Queue
Register File
Dispatch
Reservation
Stations
Load/Store
Branch
Integer
Integer FP
Forwarding Bypass
Reorder Buffer
Data
Cache
Commit
Ch. 3: Computer Organization Fundamentals

40. Questions?
Ch. 3: Computer Organization Fundamentals