1. Computer Organization CS224 Fall 2012 Lessons 7 and 8

2. addi$sp, $sp, 4#$sp = $sp + 4 slti $t0, $s2, 15#$t0 = 1 if $s2<15  Machine format (I format): MIPS Immediate Instructions 0x0A 18 8 0x0F  Small constants are used often in typical code  Possible approaches? l put “typical constants” in memory and load them l create hard-wired registers (like $zero) for constants like 1 l have special instructions that contain constants !  The constant is kept inside the instruction itself! l Immediate format limits values to the range +2 15 –1 to -2 15 §2.5 Representing Instructions in the Computer

3. More than one instruction format?  Remember Design Principle #1: Simplicity favors regularity (regularity => simplicity => clean implementation and fast performance)  Thus, ISA designers would like to keep just one instruction format  But to accommodate reasonable-size constants, field width of more than 5-bits is needed (addi, lw, sw,…)  Also, ISA designers would like to keep all instructions the same length  The compromise was to add a new instruction format (I-type), with 16-bit constant field  Design Principle #4: Good design demands good compromises

4. MIPS (RISC) Design Principles  Simplicity favors regularity l fixed size instructions l small number of instruction formats l opcode always the first 6 bits  Smaller is faster l limited instruction set l limited number of registers in register file l limited number of addressing modes  Make the common case fast l arithmetic operands from the register file (load-store machine) l allow instructions to contain immediate operands  Good design demands good compromises l e.g. 3 instruction formats, size of register file

5. Logical Operations  Instructions for bitwise manipulation OperationCJavaMIPS Shift left<< sll Shift right>>>>> srl Bitwise AND&& and, andi Bitwise OR|| or, ori Bitwise NOT~~ nor  Useful for moving, extracting and inserting groups of bits in a word §2.6 Logical Operations

6. Shift Operations  shamt: how many positions to shift  Shift left logical l Shift left and fill with 0 bits sll by i bits multiplies by 2 i  Shift right arithmetical l Shift right and fill with sign bit sra by i bits divides by 2 i (signed numbers) oprsrtrdshamtfunct 6 bits 5 bits

7. MIPS Shift Operations  Need operations to pack and unpack 8-bit characters into 32-bit words, e.g. to isolate bits 23-16 from $s0[31:0], do:  Shifts move all the bits in a word left or right sll $t2, $s0, 8#$t2 = $s0 << 8 bits srl $s0, $t2, 24#$s0 = $t2 >> 24 bits  Instruction Format (R format)  Such shifts are called logical because they fill with zeros l Notice that a 5-bit shamt field is enough to shift a 32-bit value 2 5 – 1 or 31 bit positions 0 16 10 8 0x00

8. MIPS Logical Operations  There are a number of bit-wise logical operations in the MIPS ISA and $t0, $t1, $t2#$t0 = $t1 & $t2 or $t0, $t1, $t2#$t0 = $t1 | $t2 nor $t0, $t1, $t2#$t0 = not($t1 | $t2)  Instruction Format (R format) andi $t0, $t1, 0xFF00#$t0 = $t1 & ff00 ori $t0, $t1, 0xFF00#$t0 = $t1 | ff00  Instruction Format (I format) 0 9 10 8 0 0x24 0x0D 9 8 0xFF00

9. OR Operations  Useful to include bits in a word l Set some bits to 1, leave others unchanged or $t0, $t1, $t2 # $t1 is the “ OR mask ” 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 $t2 $t1 0000 0000 0000 0000 0011 1101 1100 0000 $t0

10. AND Operations  Useful to mask bits in a word l Clear some bits to 0, leave others unchanged and $t0, $t1, $t2 # $t1 is the “ AND mask ” 0000 0000 0000 0000 0000 1101 1100 0000 0000 0000 0000 0000 0011 1100 0000 0000 $t2 $t1 0000 0000 0000 0000 0000 1100 0000 0000 $t0

11. NOT Operations  Useful to invert bits in a word l Change 0 to 1, and 1 to 0  MIPS has NOR 3-operand instruction l a NOR b == NOT ( a OR b ) nor $t0, $t1, $zero 0000 0000 0000 0000 0011 1100 0000 0000 $t1 1111 1111 1111 1111 1100 0011 1111 1111 $t0 Register 0: always read as zero

12. Conditional Operations  Branch to a labeled instruction if a condition is true l Otherwise, continue sequentially  beq rs, rt, L1 l if (rs == rt) branch to instruction labeled L1;  bne rs, rt, L1 l if (rs != rt) branch to instruction labeled L1;  j L1 l unconditional jump to instruction labeled L1 §2.7 Instructions for Making Decisions

13.  MIPS conditional branch instructions: bne $s0, $s1, Ll#go to Ll if $s0  $s1 beq $s0, $s1, Ll#go to Ll if $s0=$s1 Ex: if (i==j) h = i + j; bne $s0, $s1, L1 add $s3, $s0, $s1 L1:... MIPS Control Flow Instructions  Instruction Format (I format): 0x05 16 17 16 bit offset  How is the branch destination address specified?

14. Specifying Branch Destinations  Use a register (like in lw and sw) added to the 16-bit offset l which register? Instruction Address Register (the PC) -its use is automatically implied by instruction -PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction l limits the branch distance to -2 15 to +2 15 -1 (word) instructions from the (instruction after the) branch instruction, but most branches are local anyway PC Add 32 offset 16 32 00 sign-extend from the low order 16 bits of the branch instruction branch dest address ? Add 4 32

15. Compiling If Else Statements  C code: if (i==j) f = g+h; else f = g-h; l f, g, … in $s0, $s1, …  Compiled MIPS code: bne $s3, $s4, Else add $s0, $s1, $s2 j Exit Else: sub $s0, $s1, $s2 Exit: … Assembler calculates addresses

16. Compiling Loop Statements  C code: while (save[i] == k) i += 1; l i in $s3, k in $s5, address of save in $s6  Hand “compiled” MIPS code: Loop: sll $t1, $s3, 2 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, 1 j Loop Exit: …  An optimizing compiler will reduce this loop from 6 instructions to 3 (50% speedup). How? Bottom test_&_branching (back up, or out) saves 1 t1<- t1+4 (instead of sll, add, & addi) saves 2

17.  We have beq, bne, but what about other kinds of branches (e.g., branch-if-less-than)? For this, we need yet another instruction, slt  Set on less than instruction: slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1else # $t0 = 0  Instruction format (R format):  Alternate versions of slt slti $t0, $s0, 25# if $s0 < 25 then $t0=1... sltu $t0, $s0, $s1# if $s0 < $s1 then $t0=1... sltiu $t0, $s0, 25# if $s0 < 25 then $t0=1... 2 In Support of Branch Instructions 0 16 17 8 0x24

18. Signed vs. Unsigned  Signed comparison: slt, slti  Unsigned comparison: sltu, sltui  Example l $s0 = 1111 1111 1111 1111 1111 1111 1111 1111 l $s1 = 0000 0000 0000 0000 0000 0000 0000 0001 l slt $t0, $s0, $s1 # signed -–1 < +1  $t0 = 1 l sltu $t0, $s0, $s1 # unsigned -+4,294,967,295 > +1  $t0 = 0

19. More Branch Instructions  Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions less than blt $s1, $s2, Label less than or equal to ble $s1, $s2, Label greater than bgt $s1, $s2, Label great than or equal to bge $s1, $s2, Label slt $at, $s1, $s2#$at set to 1 if bne $at, $zero, Label#$s1 < $s2  Such branches are included in the instruction set as pseudo-instructions. These are recognized (and expanded) by the assembler Its why the assembler needs a reserved register ( $at )

20. Branch Instruction Design  Why not include blt, bge, etc in the actual MIPS ISA?  Hardware for <, ≥, … slower than =, ≠ l Combining with branch involves more work per instruction, requiring a slower clock l All instructions would be penalized!  beq and bne are the common case (Principle #3)  This is a good design compromise (Principle #4)